Fan-In Wafer Package Structure for Equipotential Electroplating
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Solution Overview
Problem
During wafer sputtering processing, electrostatic ions cause breakdown and abnormal electric discharge, leading to hidden crack points and non-uniform electroplating, which affects the normal operation and yield of wafers due to electrostatic ion bombardment and mismatched thermal expansion coefficients of materials.
Innovation Solution
A fan-in package structure is prepared by forming metal posts that penetrate through the wafer's front and back surfaces, creating an equipotential and enhancing electroplating uniformity, heat dissipation, and edge strength, while preventing electrostatic discharge and thermal warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If sputter-deposition is performed on wafer surface, then thin film can be formed, but electrostatic ion bombardment causes wafer breakdown and hidden crack points
Solution Approach 1:
The patent applies equipotentiality by forming conductive layers (such as molybdenum or tungsten layers) at specific positions on the wafer structure, including at the back surface and within the pixel structure, to create equipotential regions that prevent electrostatic charge accumulation and ion bombardment damage during sputter-deposition processing
2Manufacturing precision
If electroplating is performed on wafer, then circuit layer can be formed, but non-uniform electroplating occurs due to electrostatic discharge
Solution Approach 1:
The patent implements equipotentiality by creating conductive pathways and grounding structures that equalize the electrical potential across the wafer surface during electroplating, preventing abnormal electric discharge and ensuring uniform metal deposition throughout the circuit layer
Solution Approach 2:
The patent introduces intermediary conductive layers and grounding structures that act as mediators between the electroplating bath and the wafer, controlling the distribution of electrical current and preventing direct electrostatic discharge that would cause non-uniform plating
3Adaptability or versatility
If various materials are used in wafer manufacturing, then functional requirements can be met, but mismatched thermal expansion coefficients cause non-uniform stress release and wiring layer non-uniformity
Solution Approach 1:
The patent addresses thermal expansion mismatch by carefully selecting materials with compatible thermal expansion coefficients for layers that will be thermally processed together, and by controlling processing parameters such as heating rates and temperature profiles to minimize stress-induced non-uniformity in the wiring layer
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents wafer breakdown, abnormal discharge, and non-uniform electroplating, improving the operational reliability, heat dissipation, and electroplating efficiency while reducing thermal warpage and enhancing edge strength.
Implementation Method 1
the metal posts penetrate through the front surface and the back surface of the wafer, so that the front surface and the back surface of the wafer realize equipotential
Implementation Method 2
Sputter-deposition refers to a method in which high-energy particles are used to bombard a target material, to make atoms in the target material to be sputtered out and deposited on a surface of a substrate to form a thin film
Implementation Method 3
forming a circuit layer covering the metal posts on the first dielectric layer by electroplating
Data Source
AI summary
The present disclosure provides a preparation method of a fan-in package structure and a fan-in package structure, relating to the technical field of semiconductor packaging. In this method, holes are provided in an edge region of a wafer, a conductive metal is deposited to form metal posts, then after a protective layer and a first dielectric layer are sequentially prepared, a circuit layer is formed by electroplating, and then a second dielectric layer and a conductive bump are formed, wherein the metal posts penetrate through a front surface and a back surface of the wafer, so that the front surface and the back surface of the wafer realize equipotential.