Fan-In Semiconductor Substrate Planar Downsizing

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Solution Overview

Problem

Conventional resin-sealed semiconductor devices are limited in downsizing in the planar direction due to the arrangement of terminal portions and the need for a Fan-Out configuration, which restricts further miniaturization.

Innovation Solution

A substrate configuration with external and internal terminal portions arranged on a metal base plate, where external terminals are located within a predetermined area with the semiconductor element and internal terminals connected via wire bonding or flip-chip mode, allowing for significant downsizing while maintaining reliable connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If terminal portions are arranged outside the periphery of the die pad in a conventional Fan-Out configuration, then reliable electrical connections can be established, but the device cannot be significantly downsized in the planar direction

Engineering Contradiction:

Improveelectrical connection reliabilityVSAvoiddevice planar area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent transitions from a conventional Fan-Out configuration where terminal portions are arranged outside the die pad periphery to a Fan-In configuration where terminal portions are arranged inside the die pad periphery. This dimensional reorganization allows the external terminals to be positioned within the previously unused space under the semiconductor element, achieving planar downsizing while maintaining electrical connection reliability through alternative wiring paths.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent nests the external terminal portions within the boundary defined by the die pad periphery. By positioning terminal portions 70 inside the die pad area rather than outside, the structure effectively nests components within each other's spatial envelopes, maximizing space utilization and reducing the overall device footprint in the planar direction.

Inventive Principle:

Principle #7Nested doll (Nesting)

2Length of moving object

If the base plate is removed to reduce device thickness, then the device can be thinned substantially, but unwanted peeling between the resin sealing portion and terminal portions may occur

Engineering Contradiction:

Improvedevice thicknessVSAvoidbonding reliability

Core Design Contradiction:

Length of moving objectVSReliability

Solution Approach 1:

The patent incorporates projection portions 70t on the terminal portions and 75t on the die pad before the base plate removal process. These projections act as preventive measures that cushion against the peeling forces that will occur when the base plate is removed, distributing mechanical stress and preventing unwanted separation between the resin sealing portion and terminal portions.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The projection portions are designed to counteract the peeling force that arises during base plate removal. By having these mechanical interlocking features in place beforehand, the structure creates preliminary anti-action against the harmful peeling effect, ensuring bonding reliability is maintained even after base plate removal.

Inventive Principle:

Principle #9Preliminary anti-action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enables the semiconductor device to be significantly downsized in the planar direction while ensuring reliable electrical connections and preventing unwanted phenomena like short circuits, by using an external insulating layer and appropriate metallic materials for the terminal portions and wiring.

Implementation Method 1

a base plate made of a metal; wiring portions, respectively connecting the internal terminal portions with the external terminal portions in the plane on the base plate

Methodology Applied

Scientific EffectElectrical Conductivity: Conduction (electrical)

Implementation Method 2

a resin sealing portion sealing the internal terminal portions, external terminal portions, semiconductor element, internal connection parts and wiring portions

Methodology Applied

Scientific EffectPhysical Containment: Physical Containment

Data Source

PatentUS7947598B2Substrate for semiconductor device, resin-sealed semiconductor device, method for manufacturing said substrate for semiconductor device and method for manufacturing said resin-sealed semiconductor device

Publication Date: 2011.05.24 DAI NIPPON PRINTING CO LTD

AI summary

A substrate for a semiconductor device includes: a base plate, a plurality of external terminal portions respectively arranged in a plane on the base plate and having external terminal faces respectively facing the base plate; a plurality of internal terminal portions, respectively arranged in the plane on the base plate and having internal terminal faces respectively facing an opposite side to the base plate. The internal terminal portions are connected with the external terminal portions via wiring portions, respectively. A part of the external terminal portions are located on the base plate in a predetermined arrangement area in which a semiconductor element is arranged.