Fan-Out Package Alignment Marks for Dense I/O Redistribution
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing miniaturization of semiconductor dies and the need for higher I/O pad density in semiconductor packaging pose challenges, including limited pad numbers due to pitch constraints and the risk of solder bridges, as well as inefficiencies in packaging technologies that restrict the redistribution of I/O pads.
Innovation Solution
The development of an Integrated Fan-Out (InFO) package with alignment marks featuring grating patterns, which allows for the redistribution of I/O pads over a larger area, enabling increased pad density and improved alignment accuracy through the use of elongated and narrower grating strips for alignment marks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the pitch of the I/O pads is decreased to increase pad density, then the number of I/O pads that can be packed increases, but solder bridges may occur
Solution Approach 1:
The patent transitions from a two-dimensional pad layout directly on the die surface to a three-dimensional fan-out structure where pads are redistributed onto an organic substrate. This dimensional change allows pads to be spread over a larger area while maintaining fine pitch, thereby increasing pad count without proportionally increasing die area and reducing solder bridge risk through better spatial distribution.
Solution Approach 2:
The organic substrate acts as an intermediary between the die and the external environment. It receives the fine-pitch pads from the die, redistributes them over a larger area, and provides a stable mounting surface. This intermediary structure enables fine-pitch packaging while minimizing solder bridge formation by separating adjacent pad locations.
2Ease of manufacture
If fan-in packaging is used to maintain simple structure, then manufacturing is easier, but the number of I/O pads is limited due to die area constraints
Solution Approach 1:
The patent employs fan-out packaging that extends the pad layout from the limited two-dimensional die surface into a three-dimensional configuration using an organic substrate. This allows the pad array to spread laterally beyond the die boundaries, dramatically increasing the number of I/O pads that can be accommodated while maintaining manageable manufacturing processes.
Solution Approach 2:
The packaging structure is segmented into distinct functional layers: the die, the organic substrate, and the redistributed pad array. This segmentation allows the pad distribution function to be separated from the die, enabling independent optimization of pad density on the die and pad spacing on the substrate, thereby increasing total pad count without complicating the overall manufacturing flow.
3Measurement precision
If alignment marks with larger area are used to improve alignment accuracy, then alignment precision increases, but clarity under multiple dielectric layers deteriorates
Solution Approach 1:
The alignment mark structure employs local quality variations through multi-layer construction with alternating light-transmissive and light-reflective layers. Specific local regions (the grating patterns) are designed with enhanced optical contrast properties, allowing these localized features to provide high alignment accuracy while the overall mark structure remains detectable through multiple dielectric layers via differential light interaction.
Solution Approach 2:
The alignment mark utilizes optical property changes rather than simple area expansion. The alternating light-transmissive and light-reflective layers create strong optical contrast (analogous to color change) that enhances detectability through dielectric layers. This optical contrast mechanism allows the alignment mark to maintain high clarity and detection accuracy despite being viewed through multiple opaque or semi-opaque dielectric layers.
Data Source
AI summary
A method includes encapsulating a device die in an encapsulating material, forming a first dielectric layer over the device die and the encapsulating material, forming first redistribution lines extending into the first dielectric layer to electrically couple to the device die, forming an alignment mark over the first dielectric layer, wherein the alignment mark includes a plurality of elongated strips, forming a second dielectric layer over the first redistribution lines and the alignment mark, and forming second redistribution lines extending into the second dielectric layer to electrically couple to the first redistribution lines. The second redistribution lines are formed using the alignment mark for alignment.