Fan Out Buildup Substrate Stackable Package
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Solution Overview
Problem
The challenge is to minimize the thickness and mounting area of electronic component packages while maintaining high density interconnects to enable efficient stacking without increasing thickness, as traditional side-by-side arrangements are not feasible for compact device designs.
Innovation Solution
A fan out buildup substrate stackable package is developed, featuring a package body enclosing an electronic component with a die side buildup dielectric layer and circuit pattern, through vias connecting both sides, allowing for thin and high-density interconnects that enable additional devices to be stacked, thereby reducing overall thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If electronic component packages are stacked one upon another to reduce mounting area, then the mounting area required is reduced, but the thickness of the assembly increases
Solution Approach 1:
The patent transitions from traditional planar (2D) side-by-side mounting to three-dimensional (3D) stacking architecture. By implementing vertical stacking with multiple layers of electronic components interconnected through through-vias, the design exploits the third dimension (height/depth) to achieve higher integration density while maintaining compact form factor, thus reducing mounting area without proportionally increasing overall thickness.
Solution Approach 2:
The patent employs a nested structure where electronic components are stacked vertically one upon another, with lower layers embedded within or supporting upper layers. The package body encapsulates multiple components in a nested arrangement, with interconnection structures (through-vias, conductive layers) penetrating through outer layers to establish electrical connections to inner layers, enabling space-efficient vertical integration.
2Length of stationary object
If the thickness of electronic component packages is minimized, then the overall device size is reduced, but the capability to stack additional devices is limited
Solution Approach 1:
The patent divides the electronic system into multiple discrete functional modules or components that can be independently designed, manufactured, and stacked. Each component layer can be optimized for specific functions while maintaining standardized interconnection interfaces (through-vias, bond pads), enabling modular vertical stacking. This segmentation allows thin individual components to be combined into a compact multi-layer assembly with enhanced functionality.
Solution Approach 2:
The patent implements universal interconnection structures (through-vias, conductive patterns, bond pads) that can accommodate multiple stacking configurations and device types. The package design provides standardized mechanical and electrical interfaces that enable different component layers to be stacked in various arrangements, enhancing adaptability and versatility for different application requirements while maintaining thin profile.
3Productivity
If high density interconnects are implemented to enable efficient stacking, then the stacking efficiency is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent implements through-vias and conductive interconnection structures during the initial package fabrication process, before final component assembly. By pre-forming these interconnect pathways through the package body and substrate layers in advance, the design enables subsequent rapid stacking of electronic components without requiring complex post-assembly routing or connection operations, thus improving stacking efficiency while managing manufacturing complexity through process sequencing.
Data Source
AI summary
A fan out buildup substrate stackable package includes an electronic component having an active surface having bond pads. A package body encloses the electronic component. A first die side buildup dielectric layer is applied to the active surface of the electronic component and to a first surface of the package body. A first die side circuit pattern is formed on the first die side buildup dielectric layer and electrically connected to the bond pads. Through vias extend through the package body and the first die side buildup dielectric layer, the through vias being electrically connected to the first die side circuit pattern. The fan out buildup substrate stackable package is extremely thin and provides a high density interconnect on both sides of the package allowing additional devices to be stacked thereon.