Fan-Out Semiconductor Package Core Structure for Warpage Control
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Solution Overview
Problem
Fan-out semiconductor packages face challenges in minimizing warpage due to differences in physical properties of materials used, which affects manufacturing consistency and quality, especially during panel-level and package-level production.
Innovation Solution
Incorporating a core member with a through hole and dummy structures within the core member, which helps control thermal expansion coefficients and provides additional rigidity, thereby reducing warpage by offsetting local thermal expansion differences and enhancing uniformity of the encapsulant thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If fan-out semiconductor package uses multiple materials with different physical properties, then functionality and miniaturization are improved, but warpage occurs due to thermal expansion differences
Solution Approach 1:
The patent applies local quality by introducing dummy structures at specific locations within the core member to provide localized compensation for thermal expansion differences. These dummy structures are strategically positioned in regions where warpage is most likely to occur, allowing different parts of the package to have different structural characteristics that collectively reduce overall warpage while maintaining miniaturization.
Solution Approach 2:
The patent employs composite material principles by combining multiple materials (semiconductor chip, encapsulant, core member, dummy structures) with different physical properties into a unified package structure. The dummy structures are made of materials selected to have thermal expansion coefficients that compensate for the differences between other package materials, creating a composite system that maintains dimensional stability despite material diversity.
2Manufacturing precision
If fan-out semiconductor package uses dummy structures to reduce warpage, then manufacturing consistency is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the core member into functional regions: areas with dummy structures for warpage control and areas without for electrical functionality. This segmentation allows the package to address warpage in specific critical regions while maintaining simplicity in other areas, thereby improving manufacturing consistency without unnecessarily increasing overall device complexity.
Solution Approach 2:
The dummy structures function as sacrificial or non-functional elements whose sole purpose is to control warpage during manufacturing and operation. They do not need to be complex or expensive; simple geometric shapes made from appropriate materials suffice. These dummy structures fulfill their warpage compensation function without requiring complex interconnections or additional functionality, thus improving manufacturing consistency while minimizing added complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively reduces warpage in fan-out semiconductor packages, ensuring consistent quality and manufacturing efficiency by controlling thermal expansion and improving the structural integrity of the package.
Implementation Method 1
Incorporating a core member with a through hole and dummy structures within the core member, which helps control thermal expansion coefficients and provides additional rigidity, thereby reducing warpage by offsetting local thermal expansion differences
Implementation Method 2
Incorporating a core member with a through hole and dummy structures within the core member, which helps control thermal expansion coefficients and provides additional rigidity, thereby reducing warpage
Data Source
AI summary
A fan-out semiconductor package includes a core member having a through hole, at least one dummy structure disposed in the core member, a semiconductor chip disposed in the through hole and including an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, an encapsulant sealing at least a portion of each of the core member and the semiconductor chip, and filing at least a portion of the through hole, and a connection member disposed on the core member and the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the connection pad.