Fan-Out Package Guard Ring for Encapsulation Defect Control

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Solution Overview

Problem

The challenge in the electronics industry is to control the number of solder balls on semiconductor chips as they decrease in size, making it difficult to maintain reliable connections in smaller and lighter electronic devices, which existing technologies have not adequately addressed.

Innovation Solution

A fan-out semiconductor package is proposed, featuring a frame substrate with a through hole, a semiconductor chip, an encapsulation layer, and a guard ring on the passivation layer, which helps in preventing the outflow of encapsulation material and reducing package defects by ensuring the guard ring's top surface is at or higher than the encapsulation layer's top surface.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Weight of moving object

If semiconductor chips decrease in size to make electronic devices smaller and lighter, then the portability of electronic devices is improved, but the control of solder ball number and connection reliability deteriorates

Engineering Contradiction:
Improveweight of electronic deviceVSAvoidconnection reliability
Core Design Contradiction:
Weight of moving objectVSReliability

Solution Approach 1:

The patent introduces a fan-out semiconductor package structure as an intermediary between the semiconductor chip and the external environment. This package includes a substrate with enlarged connection pads that extend beyond the chip boundaries, allowing for better mechanical support and electrical connection reliability even as the chip size decreases. The package acts as a mediator that compensates for the reduced size of the chip while maintaining connection integrity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If the space between solder balls is determined by standards, then the standardization of semiconductor manufacturing is improved, but the flexibility in controlling the number of solder balls deteriorates

Engineering Contradiction:
Improvemanufacturing standardizationVSAvoidflexibility in solder ball configuration
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent segments the connection structure into multiple components: the semiconductor chip, the fan-out package substrate, and the solder balls. By separating the chip design from the package design, the invention allows the package substrate to be configured with varying numbers and arrangements of solder balls independent of the chip's standard dimensions. This segmentation enables flexibility in solder ball configuration while maintaining standardized chip manufacturing processes.

Inventive Principle:
Principle #1Segmentation

3Reliability

If encapsulation material is used to protect the semiconductor chip, then the protection of the chip is improved, but the outflow of encapsulation material causes defects

Engineering Contradiction:
Improvechip protectionVSAvoidencapsulation material outflow
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent implements preliminary protective measures by designing the fan-out package structure with defined boundaries and confinement features before the encapsulation process. The package substrate and its structural elements are pre-configured to contain the encapsulation material, preventing outflow during subsequent manufacturing or operational processes. This preliminary structural design eliminates the harmful effect of material outflow while maintaining the protective function.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12159833B2Fan-out semiconductor packages
Publication Date: 2024.12.03 SAMSUNG ELECTRONICS CO LTD
  • US12159833B2 patent drawing
  • US12159833B2 patent drawing
  • US12159833B2 patent drawing

AI summary

A fan-out semiconductor package includes a frame substrate having a through hole therein, a semiconductor chip in the through hole, wherein the semiconductor chip includes a chip body, a chip pad on a surface of the chip body and a passivation layer on the chip body and on the chip pad, an encapsulation layer on side surfaces of the semiconductor chip within the through hole, and a guard ring on the passivation layer and on an edge portion of the chip body.