3D Fan-Out IC Package Structure for Compact PCB Integration
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Solution Overview
Problem
The semiconductor industry faces challenges in miniaturization, higher speed, greater bandwidth, lower power consumption, and latency, which require innovative packaging techniques for semiconductor dies.
Innovation Solution
The development of a standalone three-dimensional (3D) integrated fan-out (InFO) package and printed circuit board (PCB) structure, which involves forming a carrier substrate with a buffer layer, attaching integrated circuit dies, forming redistribution layers, and connecting the structure to a PCB for enhanced mechanical support and miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional packaging techniques are used, then manufacturing process is simple, but device size cannot be sufficiently reduced
Solution Approach 1:
The patent implements fan-out wiring that extends laterally beyond the die boundaries in the x-y plane, allowing I/O connections to be made at locations outside the original die footprint. This dimensional expansion enables reduced package size while maintaining electrical connectivity requirements.
Solution Approach 2:
The patent embeds multiple functional layers within the package structure, including redistribution layers, interconnect layers, and shielding layers nested within each other. The shield layer is positioned between signal traces and the substrate, creating a nested configuration that provides EMI shielding while maintaining compact dimensions.
2Quantity of substance
If minimum feature size is reduced to increase integration density, then more components can be integrated, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the interconnect structure into multiple discrete layers with distinct functions: signal transmission layers, shielding layers, and redistribution layers. Each layer can be independently patterned and controlled, allowing manufacturing processes to target specific layer thicknesses and patterns rather than requiring all features to meet the most stringent dimensions simultaneously.
Solution Approach 2:
The patent applies different material properties and structural characteristics to different regions of the package. The shield layer uses conductive or magnetic materials positioned specifically where EMI protection is needed, while other regions use standard dielectric materials. This localized approach allows optimization of specific areas without increasing overall manufacturing precision requirements.
3Volume of moving object
If stacked semiconductor devices are used for miniaturization, then form factor is reduced, but mechanical strength and reliability may be compromised
Solution Approach 1:
The patent combines multiple functional elements into an integrated package structure where the substrate, die, redistribution layers, and shielding layers form a unified mechanical assembly. The substrate serves as both the mounting platform and the structural backbone, while the embedded layers provide both electrical functionality and mechanical reinforcement, creating a consolidated structure that maintains strength while reducing overall size.
Data Source
AI summary
An integrated circuit structure and method of forming is provided. A die is placed on a substrate and encased in molding compound. A redistribution layer is formed overlying the die and the substrate is removed. One or more surface mounted devices and/or packages are connected to the redistribution layer on an opposite side of the redistribution layer from the die. The redistribution layer is connected to a printed circuit board.