Fan-Out Interconnect for Transducer Probe Footprint Reduction

The patent introduces an interconnect layer as an intermediary component between the acoustic stack and the ASIC. This interconnect has a different pitch than either the acoustic stack elements or the ASIC contacts, acting as a mediator that enables electrical coupling without requiring pitch matching. The interconnect includes transformation sections that gradually transition from one pitch to another, allowing the decoupling of the pitch constraints while maintaining reliable electrical connections.

The patent utilizes the vertical dimension by implementing a multilayer interconnect structure. Instead of trying to match pitches in the horizontal plane, the solution moves to the vertical dimension with multiple interconnect layers that provide pitch transformation. This dimensional transition allows the ASIC to be positioned with a different horizontal pitch while maintaining electrical coupling through the vertically stacked interconnect structure.

The patent relocates I/O connectors from the peripheral horizontal plane to the vertical dimension by routing them through the interconnect layers. The I/O connectors are positioned on the backside or side of the interconnect structure, allowing accessibility while maintaining a compact footprint. This vertical routing eliminates the need for large overhead areas around the active region.

The patent nests the I/O connector routing within the interconnect structure itself. The I/O connections are integrated into the multilayer interconnect architecture, with routing paths that go through internal layers rather than occupying external peripheral space. This nesting allows the I/O functionality to be contained within the existing structure without adding overhead area.