Heterogeneous Fan-Out Interposer Layout for Compact 3D Packaging
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing the physical size of semiconductor devices while maintaining performance, as traditional packaging techniques struggle with miniaturization, higher speed, and lower power consumption, especially in stacked and bonded devices where bonding processes are complex and inefficient.
Innovation Solution
A heterogeneous fan-out structure with embedded through interposer vias and a back-side redistribution layer is introduced, involving a carrier substrate with an adhesive layer and die attach film, where a semiconductor device and ring (interposer) are attached and encapsulated, allowing for efficient heat transfer and reduced material usage, and featuring conductive pillars and dielectric layers for electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional packaging techniques are used for stacked semiconductor devices, then bonding processes can be simplified, but device size reduction and performance enhancement are limited
Solution Approach 1:
The patent divides the semiconductor device into multiple separate dies stacked vertically, each die being packaged independently before stacking. This segmentation allows each die to be processed separately through standard packaging techniques, avoiding the need for complex bonding processes while achieving compact 3D integration and reduced overall device volume
Solution Approach 2:
The patent implements a fan-out wafer level packaging (FOWLP) structure where multiple dies are nested within a single package substrate. The dies are arranged in a stacked configuration within the package, with each die encapsulated and connected through the substrate, enabling space-efficient integration without complex bonding
2Manufacturing precision
If minimum feature size is reduced to increase integration density, then more components can be integrated, but manufacturing precision requirements increase
Solution Approach 1:
The patent uses fan-out technology to extend the connection area beyond the die boundaries. By routing connections outward to a larger package area, the design achieves high integration density without requiring proportionally smaller feature sizes, effectively decoupling integration capacity from minimum feature size constraints
Solution Approach 2:
The patent transitions from planar 2D integration to 3D stacked integration. By stacking multiple dies vertically and using through-substrate vias for inter-die connections, the design achieves higher integration density in the vertical dimension without further reducing horizontal feature sizes, thereby avoiding the manufacturing precision challenges of sub-20nm nodes
3Volume of moving object
If stacked semiconductor devices are used to reduce physical size, then device volume decreases, but heat management becomes more challenging
Solution Approach 1:
The patent introduces a package substrate as an intermediary thermal management structure. The substrate incorporates thermal vias and heat spreader layers that conduct heat away from the stacked dies. This intermediary structure provides dedicated thermal pathways without requiring direct modification of the die stacking configuration, effectively managing heat in the compact 3D structure
Data Source
AI summary
A semiconductor device and method of manufacture are provided whereby an interposer and a first semiconductor device are placed onto a carrier substrate and encapsulated. The interposer comprises a first portion and conductive pillars extending away from the first portion. A redistribution layer located on a first side of the encapsulant electrically connects the conductive pillars to the first semiconductor device.