Fan-Out Wafer Level LED Package Method for High-Speed Assembly
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Solution Overview
Problem
Conventional light-emitting diode package methods, such as wire bonding, face challenges in production speed, yield rate, volume reduction, impedance, and meeting the requirements of light, thin, small, and high brightness, especially with the increasing miniaturization of LED chips, which leads to instability and inefficiencies in chip transfer and production costs.
Innovation Solution
A fan-out wafer level light-emitting diode package method where LED chips are packaged directly on a wafer protective film, involving steps like encapsulation, drilling, forming leading electrodes, cutting, sorting, constructing a package body, forming common electrodes and circuits, and adding a circuit protection layer, without the need for a package substrate, utilizing printing technology to improve efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wire bond method is used to connect LED electrodes and package substrate, then electrical connection is achieved, but production speed is slow and yield rate is low due to one-by-one bonding requirement
Solution Approach 1:
The patent segments the packaging process into two distinct stages: first, forming a wafer-level package containing multiple LED chips with their respective encapsulants; second, mounting the entire wafer package as a single unit onto the package substrate. This segmentation eliminates the need for individual wire bonding of each chip, thereby dramatically improving production speed while maintaining electrical connection quality.
Solution Approach 2:
The patent performs preliminary actions by pre-forming the wafer package structure with all necessary encapsulants, blind holes, and internal wiring before mounting. The electrical connections and protective encapsulation are established in advance at the wafer level, allowing the entire assembly to be mounted as one unit rather than assembling individual components on the substrate.
2Volume of moving object
If wire bond method is used, then electrical connection is established, but volume reduction is difficult and impedance is high
Solution Approach 1:
The patent implements a nested structure where multiple LED chips are embedded within a single wafer-level encapsulant. Each chip is surrounded by its own encapsulant material, and the entire array is enclosed in a common protective package. This nested arrangement minimizes overall volume while maintaining all necessary electrical connections internally, eliminating the need for external wire bonds that would increase both volume and complexity.
3Volume of moving object
If flip chip package technology is used, then volume is reduced and light thin small requirements are met, but chip transfer stability is poor due to precise positioning requirements
Solution Approach 1:
The patent segments the positioning problem by maintaining the wafer-level organization of chips throughout the packaging process. Since chips remain in their original wafer positions and are not individually manipulated, the precise positioning requirements are eliminated. The entire wafer package is mounted as a single unit, transferring the reliability requirement from individual chip placement to the robust wafer-level mounting process.
4Manufacturing precision
If suction nozzle size is reduced to match miniaturized chips, then chip transfer precision is improved, but suction nozzle blockage and insufficient suction increase production costs
Solution Approach 1:
The patent extracts the chips from the individual transfer process by maintaining them in their wafer-mounted state throughout packaging. The chips are never removed from the wafer substrate for individual handling, eliminating the need for suction nozzles entirely. All packaging operations are performed on the wafer level, and the complete wafer package is mounted as one unit, thereby removing the suction nozzle blockage problem and associated productivity losses.
Data Source
AI summary
A fan-out wafer level light-emitting diode package method for packaging a plurality of light-emitting diode chips on a wafer protective film, the method comprising: forming a package surface layer on first electrodes of the light-emitting diode chips, and then forming a plurality of leading electrodes electrically connected to the first electrodes on the package surface layer, cutting the light-emitting diode chips, sorting and testing as well as regrouping the light-emitting diode chips, covering sides of the light-emitting diode chips with a package layer, drilling and filling a conductive material on the package layer to form a plurality of common electrodes, and then printing a plurality of common electrical circuits, electrically connecting each of the common electrical circuits to one of the common electrodes and the leading electrodes, and finally covering with a circuit protection layer to complete the process.