Fan-Out Fan-In Matrix for Parallel Device Testing

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Solution Overview

Problem

Automated test equipment requires dedicated PIN electronics channels for each device under test, leading to increased testing time and lack of electrical isolation, causing unnecessary damage to other devices during serial data reads.

Innovation Solution

A test apparatus and method that enables parallel input and output of test signals to multiple devices using a single PIN electronics channel, with a storage device to store response signals and a serial output circuit to convey data without test time overhead, providing electrical isolation between devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dedicated PIN electronics channels are used for each device under test, then data can be read from each device, but testing time increases significantly due to serial reading requirement

Engineering Contradiction:
Improvedata reading capabilityVSAvoidtesting time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the data reading process into parallel read operations across multiple devices while maintaining a single PIN electronics channel. The test apparatus divides the reading task by simultaneously reading data from multiple devices in parallel, then consolidates the results through the single channel, eliminating the need for sequential reading and reducing testing time.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a time-based sequential reading approach to a spatial parallel reading approach. By using multiple test channels that can operate simultaneously, the system reads data from multiple devices across different 'dimensions' of time, effectively parallelizing the reading process and reducing total testing time.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Device complexity

If serial data reading is used from multiple devices, then a single PIN electronics channel can be used, but electrical isolation between devices is lost causing false failures

Engineering Contradiction:
Improvechannel configurationVSAvoiddevice testing accuracy
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent introduces an intermediary buffer or latch between the devices and the PIN electronics channel. This intermediary component provides electrical isolation during the read operation, allowing data to be captured from multiple devices simultaneously without electrical interference between them. The buffer acts as a mediator that decouples the devices from each other while still enabling data transfer through the single channel.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If multiple devices are tested in parallel, then test time is reduced, but electrical isolation between devices is compromised causing cross-contamination of errors

Engineering Contradiction:
Improvetesting throughputVSAvoiderror detection accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the testing system into independent test channels, each capable of reading from specific devices. This segmentation allows parallel testing of multiple devices while maintaining electrical isolation through dedicated read paths for each device, preventing error cross-contamination while maximizing testing throughput.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS7827452B2Error catch RAM support using fan-out/fan-in matrix
Publication Date: 2010.11.02 ADVANTEST CORP
  • US7827452B2 patent drawing
  • US7827452B2 patent drawing
  • US7827452B2 patent drawing

AI summary

In accordance with one embodiment of the invention, a method and apparatus are provided for obtaining test data from multiples devices under test. This could be accomplished in accordance with one embodiment by outputting from a testing device a test signal for input in parallel to at least two devices under test; inputting in parallel to the testing device at least two response signals, each response signal produced by one of the at least two devices under test; storing the response signals received in parallel in a storage device; and serially outputting the response signals from the storage device.