3D Fan-Out Memory POP Structure for High-I/O Packaging
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Solution Overview
Problem
Traditional substrate manufacturing technologies are limited by line width/line spacing and cost, and cannot support the high integration levels required by advanced integrated circuit manufacturing, leading to increased production time and expense.
Innovation Solution
A package-on-package (POP) structure is developed, combining a three-dimensional fan-out memory package unit and a two-dimensional fan-out peripheral circuit chip SiP package unit through rewiring layers, eliminating the need for through-silicon-vias and using a molded substrate to support wire bonding, allowing for high-density and high-integration packaging with reduced line width/line spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional substrate manufacturing is used with increased substrate layers to support more chip I/Os, then the I/O capacity is improved, but the manufacturing cost and production time increase significantly
Solution Approach 1:
The patent transitions from traditional two-dimensional substrate routing to three-dimensional fan-out routing. Multiple routing layers are stacked vertically, allowing I/O signals to be distributed in three dimensions rather than confined to planar layers. This dimensional change enables higher I/O capacity without proportionally increasing substrate layer count or manufacturing complexity
Solution Approach 2:
The substrate is divided into multiple routing layers, each handling specific I/O signal groups. This segmentation allows parallel processing of different signal types and enables independent optimization of each routing layer, improving overall production efficiency while maintaining high I/O capacity
2Ease of manufacture
If traditional substrate manufacturing with minimum line width/line spacing of 20 μm/20 μm is used, then the manufacturing process is simpler, but the integration level cannot support advanced front-end chip manufacturing requirements
Solution Approach 1:
The patent modifies critical geometric parameters including reducing line width and line spacing to values significantly smaller than traditional 20 μm/20 μm minimums. The fan-out structure with controlled via dimensions and optimized trace geometries enables advanced integration levels while maintaining manufacturability through systematic parameter optimization across multiple routing layers
3Quantity of substance
If more substrate layers are added to increase chip I/O capacity, then the I/O bandwidth is improved, but the overall manufacturing cost increases
Solution Approach 1:
By implementing three-dimensional fan-out routing with vertically stacked layers, the patent achieves higher I/O bandwidth without linearly increasing the number of substrate layers. The fan-out structure allows multiple I/O paths to share common via regions, reducing the total layer count required compared to traditional layered routing approaches
Data Source
AI summary
The package-on-package (POP) structure includes a first package unit of three-dimensional fan-out memory chips and a SiP package unit of the two-dimensional fan-out peripheral circuit chip. The first package unit includes: memory chips laminated in a stepped configuration; a molded substrate; wire bonding structures; a first rewiring layer; a first encapsulating layer; and first metal bumps, formed on the first rewiring layer. The SiP package unit includes: a second rewiring layer; a peripheral circuit chip; a third rewiring layer, bonded to the circuit chip; first metal connection pillars; a second encapsulating layer for the circuit chip and the first metal connection pillars; and second metal bumps on the second rewiring layer. The first metal bumps are bonded to the third rewiring layer. Integrating the two package units into the POP is enabled by three rewiring layers and the molded substrate which supports the first package unit during wire bonding process.