Fan-Out Wafer Packaging with Metal-Paste RDL Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing fan-out wafer level packaging (FOWLP) technologies face high manufacturing costs, environmental impact, and inefficiencies due to chemical plating or electroplating processes, and require additional dies for increased efficiency and computational power, with challenges in connecting dies inside and outside the packaging unit.
Innovation Solution
A FOWLP unit is designed with a substrate, dielectric layers, and conductive circuits formed by filling metal pastes into slots and grinding, allowing for electrical connections through conductive pillars and bonding pads, reducing the need for chemical plating and electroplating, and enabling efficient electrical connections between dies and the outside.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chemical plating or electroplating is used to form conductive circuits in the RDL, then electrical extension and interconnections are achieved, but manufacturing cost increases and environmental harm is caused
Solution Approach 1:
The patent replaces the chemical/electrical plating process with a mechanical printing process. Specifically, conductive paste is printed directly onto the substrate to form conductive circuits, eliminating the need for chemical plating solutions and electroplating equipment. This substitution resolves the contradiction by maintaining electrical connectivity while removing harmful chemical processes and reducing manufacturing complexity
Solution Approach 2:
The patent changes the formation method parameter from chemical/electrical deposition to mechanical paste deposition. By using screen printing or other printing techniques to deposit conductive paste, the process parameters shift from controlling plating chemistry and electrical current to controlling paste viscosity, printing pressure, and screen mesh characteristics, thereby eliminating environmental harm while maintaining conductive circuit functionality
2Productivity
If additional dies are added to increase efficiency and computational power, then performance improves, but electrical connection complexity increases
Solution Approach 1:
The patent utilizes the XY plane dimension extensively by distributing bonding pads around the periphery of each die rather than concentrating connections underneath. This allows multiple dies to be arranged in a fan-out configuration where electrical connections extend laterally across the substrate, enabling additional dies to be integrated without increasing vertical connection complexity. The conductive circuits are routed in the horizontal plane to connect multiple dies and bond pads, effectively using dimensional space to manage connection complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method reduces manufacturing costs, environmental impact, and improves efficiency and reliability while allowing for compact design and increased chip connections, enhancing performance and market competitiveness.
Implementation Method 1
The first, the second, and the third conductive circuits are produced by filling of metal pastes into slots and grinding of the metal paste
Data Source
AI summary
A fan-out wafer-level packaging (FOWLP) unit is provided. The FOWLP unit includes a substrate, a first dielectric layer, a plurality of first conductive circuits, at least one first die, a second dielectric layer, at least one conductive pillar, a plurality of second conductive circuits, a third dielectric layer, a plurality of third conductive circuits, and at least one second die. The first die and the second die are electrically connected with the outside through first die pads around a chip area on a second surface of the first die. The first conductive circuits, the second conductive circuits, and the third conductive circuits are produced by filling of metal pastes into slots and grinding of the metal paste. Thereby problems of FOWLP technology available now generated during manufacturing of the respective conductive circuits including higher manufacturing cost and environmental unfriendly can be solved.