Thermally Enhanced Fully Molded Fan-Out Module Without Silicon Interposer
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Solution Overview
Problem
Current semiconductor packaging methods, particularly those using silicon interposers, face challenges in achieving high thermal dissipation and routing density, leading to limitations in miniaturization, assembly yield, and reliability due to warpage and CTE mismatch issues.
Innovation Solution
The development of a fully molded fan-out module (FMFOM) method that encapsulates semiconductor dies and conductive interconnects without a silicon interposer, using a temporary carrier and encapsulant to form a molded core unit with fine-pitch build-up interconnects, allowing for direct contact and high-density routing, and integrating a heat sink with thermal interface material for enhanced thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If silicon interposers are used for high routing density, then routing density is improved, but warpage and CTE mismatch issues occur leading to reduced reliability
Solution Approach 1:
The patent removes the silicon interposer from the packaging structure entirely, extracting the source of CTE mismatch and warpage problems. Instead of using a silicon interposer for routing, the invention uses direct wire bonding or flip-chip interconnects from the die pads to the package leads, eliminating the problematic intermediate silicon layer while maintaining routing functionality.
Solution Approach 2:
The package substrate serves multiple functions simultaneously: it provides mechanical support, electrical interconnection, and thermal management pathways. By integrating these functions directly into the substrate without requiring a separate silicon interposer, the design achieves high routing density while avoiding CTE mismatch issues between dissimilar materials.
2Ease of manufacture
If conventional packaging methods are used, then manufacturing is simpler, but thermal dissipation is insufficient leading to higher thermal resistance
Solution Approach 1:
The patent employs composite material structures in the packaging substrate, combining materials with different thermal and electrical properties. The substrate includes thermally conductive pathways and layers that facilitate heat extraction from the die, while maintaining electrical isolation where needed. This composite approach enables effective thermal management without complicating the manufacturing process.
Solution Approach 2:
The package substrate acts as an intermediary thermal pathway between the die and the external environment. By designing the substrate with integrated thermal vias and heat spreader layers, the invention creates efficient thermal conduction pathways that mediate heat transfer from the heat-generating die to the package casing or external heat sink, significantly reducing thermal resistance.
3Volume of moving object
If semiconductor devices are miniaturized, then power consumption and footprint are reduced, but thermal management becomes more challenging
Solution Approach 1:
The patent addresses thermal management in miniaturized devices by transitioning from planar heat dissipation to three-dimensional thermal pathways. The package substrate incorporates vertical thermal vias and multi-layer heat extraction pathways that conduct heat in the Z-direction (vertical dimension) away from the compact die, enabling effective thermal management despite the reduced horizontal footprint of the device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high thermal dissipation, improved assembly yield, reduced warpage, and lower thermal resistance, allowing for smaller, more reliable semiconductor packages with increased routing density and simplified manufacturing processes.
Implementation Method 1
integrating a heat sink with thermal interface material for enhanced thermal management
Data Source
AI summary
A semiconductor device includes a molded core unit that includes a first semiconductor die with conductive interconnects and a second semiconductor with conductive interconnects. The first semiconductor die and the second semiconductor die are encapsulated by a single encapsulant that contacts at least four sides surfaces and an active surface of the first semiconductor die and the second semiconductor die, as well as side surfaces of the conductive interconnects. The molded core unit further includes a fine-pitch build-up interconnect structure disposed over the encapsulant and coupled to the conductive interconnects of the first semiconductor die and the conductive interconnects of the second semiconductor die interconnected without a silicon interposer. The molded core unit can be mounted to an organic multi-layer substrate. A heat sink may be coupled to the back surfaces of the first semiconductor die and the second semiconductor die with a thermal interface material (TIM).