Fully Molded Fan-Out Package Warpage Reduction
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Solution Overview
Problem
Fan-out wafer level packaging processes face challenges with panel warpage and topographical discontinuities due to uneven mold compound distribution and removal, requiring extensive post-processing and complex redistribution layer construction.
Innovation Solution
A method of fully encapsulating semiconductor die units in mold compound using a compression molding process with spacer elements to create a gap between the die and the carrier, allowing for balanced mold compound distribution and eliminating the need for post-processing, while constructing fan-in and fan-out redistribution layers for electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If die units are placed face down on a temporary tape carrier and overmolded with compression molding, then the packaging process can be simplified, but panel warpage and topographical discontinuities occur due to uneven mold compound distribution
Solution Approach 1:
The patent applies preliminary action by forming a gap between the die unit and carrier before the molding process. This gap is created using spacer elements or by positioning the die unit at a specific height above the carrier, ensuring that mold compound can uniformly distribute around the die unit during compression molding, thereby preventing warpage and topographical discontinuities.
2Productivity
If the tape carrier is removed after molding to expose the active surface, then individual packages can be formed, but extensive post-processing is required to address warpage and discontinuities
Solution Approach 1:
The patent performs preliminary action by creating the gap structure before molding, which prevents warpage and topographical discontinuities during the molding process itself. This eliminates the need for extensive post-processing steps to correct these defects, thereby reducing device complexity while maintaining high productivity.
3Reliability
If a wafer level chip scale package build-up structure is formed on the reconstituted wafer, then electrical connectivity is achieved, but complex redistribution layer construction is required
Solution Approach 1:
The patent applies preliminary action by establishing the gap structure before molding, which creates a more uniform and stable package structure. This uniform structure simplifies the subsequent construction of redistribution layers, as the base structure is free from warpage and topographical discontinuities that would complicate the routing and connection processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the packaging process, reduces warpage, and eliminates the need for post-processing, resulting in a balanced package structure with improved routing flexibility and reduced manufacturing costs.
Implementation Method 1
The multiple die units and temporary tape carrier are overmolded with a molding compound using a compression molding process
Data Source
AI summary
A method for manufacturing a device package may include constructing a spacer element coupled with a surface of a semiconductor die unit, where the spacer element is configured to create a gap between the semiconductor die unit and a surface of a carrier, and encapsulating the semiconductor die unit within a mold compound, where the encapsulating includes introducing the mold compound into the gap.