Fan-Out Semiconductor Package Layout for Compact 3D SIP Integration
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving a compact size while integrating multiple pins and providing a multi-function/integration structure within a limited area, particularly with the increasing demand for highly integrated system-in-package (SIP) solutions.
Innovation Solution
A semiconductor package design utilizing a fan-out structure with a core member, through-holes, encapsulants, redistribution layers, and core vias to electrically connect multiple semiconductor chips, allowing for a PoP scheme and 3D integration, enabling efficient implementation of a highly integrated SIP.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a compact semiconductor package design is implemented, then the package size is reduced, but the integration of multiple pins and multi-function structures becomes difficult
Solution Approach 1:
The patent implements 3D stacking architecture where multiple semiconductor chips are vertically stacked and interconnected through through-silicon vias (TSVs) and redistribution layers. This vertical integration approach enables multiple pins and multi-functional structures to be packed into a compact footprint by utilizing the third dimension (height) rather than expanding horizontally, thus resolving the contradiction between small package size and high integration capability
Solution Approach 2:
The patent employs nested packaging structures where smaller chips are placed within or alongside larger chips in a hierarchical arrangement. The through-hole in the core member contains stacked chips, and redistribution layers are nested between chip layers to provide electrical interconnections. This nesting approach maximizes the use of limited space while maintaining multiple functional elements, enabling high pin count and multi-functionality in a compact package
2Adaptability or versatility
If multiple semiconductor chips are integrated in a through-hole, then integration capability is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by pre-forming through-holes and redistribution layers on substrates before chip mounting. The core member is prepared with through-holes and TSV structures in advance, and redistribution layers are patterned on substrate surfaces before chips are stacked and interconnected. This preliminary preparation simplifies the overall manufacturing process by breaking down complex multi-chip integration into manageable sequential steps, reducing manufacturing complexity while maintaining high integration capability
Data Source
AI summary
A semiconductor package includes a first package having a first semiconductor chip, a second semiconductor chip and a core member including a through-hole. At least one of the first and second semiconductor chips is disposed in the through-hole. An encapsulant is disposed in the through-hole. A first redistribution layer is disposed above the core member and is electrically connected to the first and second semiconductor chips. A second redistribution layer is disposed under the core member and electrically connects the first and second semiconductor chips with an external PCB. Core vias penetrate the core member and electrically connect the first and second redistribution layers. A second package is disposed on the first package and includes a third semiconductor chip. A plurality of first electrical connection structures electrically connects the first and second packages. A plurality of second electrical connection structures electrically connects the semiconductor package with the external PCB.