Fan-Out Package Design Eliminates Cavity Process
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Solution Overview
Problem
The cavity process used in manufacturing fan-out type electronic component packages is inefficient in terms of process cost and prone to defects, especially when dealing with multiple cavities, as it requires additional steps to remove exposed glass fibers and can lead to increased costs.
Innovation Solution
A new electronic component package design that omits the cavity process by using a first insulating layer with fiducial marks for precise component placement and a second insulating layer with redistribution conductors, allowing for precise component disposition and reduced process costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the cavity process is used to manufacture fan-out type packages, then the electronic component can be precisely disposed, but the process cost increases and defects may occur when the number of cavities is increased
Solution Approach 1:
The patent extracts and eliminates the cavity formation step from the manufacturing process. Instead of forming cavities in the CCL substrate to dispose components, the invention uses a planar substrate surface with conductive patterns directly formed on it. This removal of the cavity process step reduces manufacturing complexity and cost while maintaining component placement precision through alternative means (conductive patterns and alignment features).
Solution Approach 2:
The patent segments the manufacturing process into distinct functional layers: a substrate layer, a conductive pattern layer for electrical connection, and an encapsulant layer for protection. By segmenting the functions, the complex cavity formation process is replaced with simpler, more cost-effective processes for each layer, reducing overall manufacturing difficulty and cost while achieving the same functional outcomes.
2Manufacturing precision
If the cavity process is used to manufacture fan-out type packages, then the electronic component can be precisely disposed, but process defects may occur due to exposed glass fibers
Solution Approach 1:
The patent removes the cavity formation step that causes glass fiber exposure and subsequent defects. By using a planar substrate surface instead of cavities, the source of the defect is eliminated entirely, improving process reliability while maintaining component placement precision through the conductive pattern alignment system.
Solution Approach 2:
The patent converts the potential harm of glass fiber exposure into a benefit by using a planar surface design that inherently prevents exposure. The simplicity of the planar structure with integrated conductive patterns actually improves reliability by eliminating the complex cavity walls where glass fibers would be exposed and cause defects.
3Adaptability or versatility
If the number of cavities is increased to accommodate multiple connection terminals, then the package functionality is improved, but the process cost and complexity increase
Solution Approach 1:
The patent implements a universal planar substrate design that can accommodate any number of connection terminals without requiring additional cavity formation processes. The conductive patterns on the planar surface can be configured in various arrangements (arrays, grids, or custom patterns) to provide multiple connection terminals, making the same basic structure adaptable to different terminal requirements without increasing process complexity or cost.
Solution Approach 2:
The patent transitions from a three-dimensional cavity structure to a two-dimensional planar surface for accommodating multiple connection terminals. By arranging conductive terminals in a planar configuration rather than within vertical cavities, the design can scale to accommodate more terminals by expanding in the horizontal plane rather than requiring additional vertical space or complex multi-level cavity structures, thereby reducing manufacturing complexity.
Data Source
AI summary
An electronic component package includes a first insulating layer having a via formed therein and a pattern formed thereon, an electronic component disposed on the first insulating layer so that an inactive side thereof is directed toward the first insulating layer, and a second insulating layer disposed on the first insulating layer so as to cover the electronic component and having a redistribution pattern formed thereon so as to be electrically connected to the electronic component.


