Fan-Out Semiconductor Package Insulating Layer Via Reliability

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Solution Overview

Problem

Current fan-out semiconductor packages face challenges in forming backside circuits with reliable adhesion and surface roughness, especially when using molding materials that harden and lose physical properties, limiting the formation of via holes due to material property differences.

Innovation Solution

A fan-out semiconductor package structure that includes an insulating layer on top of the encapsulant, allowing for the formation of double via holes with a conductive via that passes through the insulating layer rather than the encapsulant, enabling independent material selection and reducing moisture absorption effects, thereby enhancing the reliability of the conductive via.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a conductive via is formed directly in the encapsulant, then the manufacturing process is simpler, but the reliability of the conductive via deteriorates due to material property differences and moisture absorption

Engineering Contradiction:
Improveease of forming conductive viaVSAvoidreliability of conductive via
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

An insulating layer is introduced as an intermediary between the encapsulant and the conductive via. This insulating layer serves as a mediator that prevents direct contact between the conductive via and the encapsulant, thereby eliminating the harmful effects of moisture absorption and material property mismatches while maintaining the manufacturing process simplicity

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The conductive via is extracted from the encapsulant material and relocated to the insulating layer. By taking out the conductive via formation process from the encapsulant, the patent eliminates the reliability issues associated with forming vias directly in the encapsulant while preserving the fan-out package structure

Inventive Principle:
Principle #2Taking out (Extraction)

2Volume of moving object

If the encapsulant material is selected for compact size, then the package size is reduced, but the ability to form reliable backside circuits deteriorates due to material hardening and loss of physical properties

Engineering Contradiction:
Improvepackage sizeVSAvoidease of forming backside circuit
Core Design Contradiction:
Volume of moving objectVSEase of manufacture

Solution Approach 1:

The insulating layer is applied to the encapsulant surface before forming the backside circuit. This preliminary action creates a suitable substrate on the encapsulant that retains the necessary physical properties for via hole formation, even when the encapsulant itself has hardened and lost its original physical properties

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the material parameter of the surface layer by applying an insulating layer with different physical properties than the encapsulant. This parameter change allows the surface to support conductive via formation while the underlying encapsulant maintains its compact size and structural integrity

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10665549B2Fan-out semiconductor package
Publication Date: 2020.05.26 SAMSUNG ELECTRONICS CO LTD
  • US10665549B2 patent drawing
  • US10665549B2 patent drawing
  • US10665549B2 patent drawing

AI summary

A fan-out semiconductor package includes: a frame, including a wiring layer, and having a through-hole; a semiconductor chip disposed in the through-hole, and including a connection pad; an encapsulant covering at least a portion of each of the frame and an inactive surface of the semiconductor chip, and having a first opening exposing at least a portion of the wiring layer; an insulating layer disposed on the encapsulant, and having a second opening formed in the first opening to expose at least a portion of the wiring layer; a conductive pattern layer disposed on the insulating layer; a conductive via disposed in the second opening; and a connection structure disposed on the frame and an active surface of the semiconductor chip, and including one or more redistribution layers. The conductive pattern layer and the redistribution layer are electrically connected to the connection pad.