Fan-Out Wafer-Level Package Structure for Stacked Chip Interconnects
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Solution Overview
Problem
The challenge in electronics design is to increase computing power and storage in a compact form, as transistor sizes have reached physical limits, requiring innovative packaging solutions to reduce interconnect distances between chips.
Innovation Solution
The fan-out wafer level package structure involves a carrier with an adhesive layer, die attachment, formation of vias, and a molded substrate with a redistribution layer to facilitate electrical connections, allowing for stacked chip configurations and package-on-package mounting with varied bond pitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If transistor sizes are reduced to increase computing power, then computing power increases, but manufacturing precision limits are reached
Solution Approach 1:
The patent transitions from planar 2D chip layouts to three-dimensional stacked chip architectures. By stacking multiple chips vertically and using through-substrate vias for interconnection, the invention enables continued scaling of computing power without further reducing transistor dimensions, thus avoiding the manufacturing precision limits of conventional planar designs.
Solution Approach 2:
The patent implements a nested structure where multiple chips are stacked within a single package substrate. Each chip layer contains functional elements, and the overall structure nests multiple functional layers vertically, allowing increased computing power within a compact volume without requiring smaller transistors.
2Length of stationary object
If chips are stacked to reduce interconnect distance, then interconnect distance decreases, but package complexity increases
Solution Approach 1:
The package substrate serves multiple functions simultaneously: it provides mechanical support for stacked chips, contains through-substrate vias for electrical interconnection, enables thermal management pathways, and facilitates signal routing. This multi-functionality reduces the need for separate components and simplifies the overall package structure despite the three-dimensional chip stacking.
3Adaptability or versatility
If bond pitch is varied for package-on-package mounting, then adaptability improves, but manufacturing complexity increases
Solution Approach 1:
The patent segments the interconnection function into multiple independent layers. The package substrate contains through-substrate vias that can be configured with different pitch patterns on different faces, allowing each package layer to have optimized bond pitches for its specific mounting requirements. This segmentation enables adaptability to different package-on-package configurations without requiring complete redesign of the entire interconnection system.
Data Source
AI summary
A method for forming a package structure may comprise applying a die and vias on a carrier having an adhesive layer and forming a molded substrate over the carrier and around the vias, and the ends of the vias and mounts on the die exposed. The vias may be in via chips with one or more dielectric layers separating the vias. The via chips 104 may be formed separately from the carrier. The dielectric layer of the via chips may separate the vias from, and comprise a material different than, the molded substrate. An RDL having RDL contact pads and conductive lines may be formed on the molded substrate. A second structure having at least one die may be mounted on the opposite side of the molded substrate, the die on the second structure in electrical communication with at least one RDL contact pad.