Fan-Out Semiconductor Package for Higher I/O and Lower Thickness
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Solution Overview
Problem
The existing package-on-package (POP) manufacturing process using copper bumps is complex and results in increased package thickness, limiting the size and number of input/output terminals due to the stacking of memory chips.
Innovation Solution
A semiconductor package design featuring a redistribution wiring layer with multiple levels of redistribution wirings, where first and second semiconductor chips are connected via conductive wires, allowing for a fan-out structure that increases the number of input/output terminals and reduces overall package thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper bumps are used to stack memory chips in a package-on-package structure, then the memory chips can be connected and stacked, but the package thickness increases and the manufacturing process becomes complicated
Solution Approach 1:
The patent transitions from vertical stacking via copper bumps to a planar fan-out structure where interconnects spread horizontally across multiple redistribution wiring layers. This dimensional shift from vertical to horizontal interconnection reduces package thickness while maintaining connection reliability through the multi-layer wiring architecture.
Solution Approach 2:
The patent extracts the copper bump stacking approach and replaces it with a redistribution wiring layer structure. By removing the vertical copper bump interconnection method and substituting it with planar redistribution wirings, the package thickness is reduced while achieving the same chip connection function through a different structural approach.
2Reliability
If memory chips are stacked using copper bumps, then chip connection is achieved, but the number of input/output terminals is limited by the chip size
Solution Approach 1:
The patent uses multiple levels of redistribution wiring layers stacked in the vertical dimension to expand the I/O terminal capacity. By utilizing the Z-axis (vertical stacking of wiring layers) rather than being constrained to the XY-plane, the package can accommodate more input/output terminals without increasing the chip footprint area.
Solution Approach 2:
The patent segments the interconnection function across multiple redistribution wiring layers, with each layer containing specific routing patterns and I/O terminals. This segmentation allows different layers to handle different signal types and terminal functions, thereby increasing the total number of available I/O terminals beyond what a single chip layer could provide.
3Reliability
If a complex copper bump stacking process is used, then memory chips can be connected, but the manufacturing complexity increases
Solution Approach 1:
The patent extracts and eliminates the copper bump formation and stacking process from the manufacturing flow. By removing this complex process entirely and replacing it with a redistribution wiring layer approach, manufacturing complexity is reduced while maintaining chip connection capability through alternative wiring structures.
Solution Approach 2:
The patent merges the chip connection function with the redistribution wiring structure, combining multiple functions (signal routing, power distribution, and inter-chip connection) into an integrated wiring layer system. This consolidation eliminates the need for separate copper bump processes and simplifies the overall manufacturing workflow.
Data Source
AI summary
A semiconductor package includes a redistribution wiring layer having redistribution wirings stacked in at least two levels; a first semiconductor chip arranged on the redistribution wiring layer; a plurality of second semiconductor chips arranged on the first semiconductor chip; first conductive wires electrically connecting first chip pads of the first semiconductor chip and the redistribution wirings of the redistribution wiring layer; second conductive wires electrically connecting second chip pads of the plurality of second semiconductor chips and the redistribution wirings of the redistribution wiring layer; and a sealing unit disposed on the redistribution wiring layer.