Fan-Out Semiconductor Package Warpage Reduction via Polymer Pattern
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Solution Overview
Problem
Fan-out semiconductor packages are prone to warpage due to high manufacturing stress, which existing technologies have not effectively addressed.
Innovation Solution
A semiconductor package design that includes a semiconductor die, encapsulant, redistribution layer, polymer pattern, and heat dissipation structure, where the polymer pattern is formed over the encapsulant surrounding the die and the heat dissipation structure is in contact with both the die and polymer pattern, effectively managing thermal expansion mismatches to reduce stress and enhance heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fan-out semiconductor packaging process is used to achieve higher integration level and greater number of external contacts, then the integration level and number of external contacts are improved, but the package is subjected to high level stress resulting in warpage issues
Solution Approach 1:
The patent applies parameter changes by modifying the coefficient of thermal expansion (CTE) of the encapsulant through adding fillers, and by designing the polymer pattern with specific CTE properties. These parameter adjustments allow the encapsulant and polymer pattern to compensate for each other's thermal expansion stresses, reducing overall warpage while maintaining the fan-out packaging structure that provides higher integration and more external contacts
Solution Approach 2:
The patent uses composite materials by incorporating fillers into the encapsulant material to adjust its CTE properties. The encapsulant becomes a composite material that combines the base polymer with filler particles, creating a material with tailored thermal expansion characteristics that match the overall package requirements and reduce warpage stress
2Stability of the object's composition
If polymer pattern is formed over encapsulant surrounding semiconductor die, then stress management is improved, but additional manufacturing steps increase device complexity
Solution Approach 1:
The patent applies merging by combining the stress management function with the existing encapsulation process. The polymer pattern is formed as part of the encapsulant structure, and the encapsulant itself serves dual purposes: providing mechanical protection and enabling stress compensation through its adjusted CTE properties. This integration reduces the need for separate stress management components
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design reduces warpage susceptibility and improves heat dissipation in semiconductor packages by managing thermal expansion stresses and ensuring effective heat dissipation through the heat dissipation structure.
Implementation Method 1
the heat dissipation structure is in contact with a back side of the semiconductor die and extends onto the polymer pattern
Implementation Method 2
the coefficient of thermal expansion (CTE) of the encapsulant is greater than the CTEs of the polymer pattern and the dielectric layers
Data Source
AI summary
A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a semiconductor die, an encapsulant, a redistribution layer, a polymer pattern and a heat dissipation structure. The semiconductor die has conductive pads at its active side, and is laterally encapsulated by the encapsulant. The redistribution layer is disposed at the active side of the semiconductor die, and spans over a front surface of the encapsulant. The redistribution layer is electrically connected with the conductive pads. The polymer pattern is disposed at a back surface of the encapsulant that is facing away from the front surface of the encapsulant. The semiconductor die is surrounded by the polymer pattern. The heat dissipation structure is in contact with a back side of the semiconductor die that is facing away from the active side, and extends onto the polymer pattern.