Fan-Out Package Structure for High-Density PoP Interconnects

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Solution Overview

Problem

The semiconductor industry faces challenges in achieving compact and efficient packaging of electronic components due to the increasing complexity and miniaturization of integrated circuits, which requires innovative methods for manufacturing package structures that enhance integration density and reduce area usage while maintaining reliability and connectivity.

Innovation Solution

The method involves forming a package structure using a carrier with a de-bonding layer, a redistribution layer (RDL) with multiple polymer and conductive layers, and a die connected via conductive bumps, followed by encapsulation and the formation of through integrated fan-out vias (TIVs) and protection layers to control warpage and facilitate electrical connections, allowing for the creation of compact and reliable package-on-package (PoP) devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If continuous reductions in minimum feature size are implemented to increase integration density, then more electronic components can be integrated into a given area, but the package size must be reduced accordingly to accommodate smaller components

Engineering Contradiction:
Improveintegration densityVSAvoidpackage area
Core Design Contradiction:
Quantity of substanceVSArea of stationary object

Solution Approach 1:

The patent implements integrated fan-out packaging that extends electrical connections in the lateral dimension through TIV structures, allowing signals to route outside the die footprint. This dimensional extension enables higher integration density without proportionally reducing package area, as connections utilize the planar space around the die rather than being confined to vertical through-holes.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The packaging structure is segmented into distinct functional layers including carrier substrate, redistribution layers, encapsulant, and TIV structures. This segmentation allows independent optimization of each layer - the carrier provides mechanical support, RDLs provide routing, and TIVs provide external connections - enabling high integration density while maintaining adequate package area for heat dissipation and signal integrity.

Inventive Principle:
Principle #1Segmentation

2Reliability

If complex multi-layer RDL structures with multiple polymer and conductive layers are formed to achieve efficient electrical redistribution, then connectivity is improved, but the manufacturing process complexity increases

Engineering Contradiction:
Improveelectrical connectivityVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The redistribution layers serve multiple functions simultaneously: they provide electrical connectivity between die pads and package terminals, enable signal routing around the die perimeter through TIVs, provide mechanical strain relief, and offer thermal management pathways. This multi-functionality reduces the need for separate dedicated structures, simplifying the overall manufacturing process despite the multi-layer complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent introduces encapsulant material as an intermediary that bonds the die to the carrier substrate and provides a matrix for forming TIV structures. This encapsulant mediates between the rigid die and carrier, allowing flexible routing of TIVs while maintaining structural integrity. The de-bonding layer acts as another intermediary that enables controlled release of the die from the carrier after bonding, simplifying the assembly process.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Area of stationary object

If through integrated fan-out vias (TIVs) are formed to enable lateral electrical connections outside the die area, then area usage is reduced, but warpage control becomes more challenging

Engineering Contradiction:
Improvearea usageVSAvoidwarpage control
Core Design Contradiction:
Area of stationary objectVSStability of the object's composition

Solution Approach 1:

The patent employs a carrier substrate with specific mechanical properties that acts as a counterweight to the warpage forces generated by TIV formation and encapsulant curing. The carrier's rigidity and thermal expansion characteristics are selected to compensate for stress buildup during processing, maintaining planarity despite the complex multi-layer structure and lateral routing requirements.

Inventive Principle:
Principle #8Anti-weight (Counterweight)

Data Source

PatentUS11862469B2Package structure and method of manufacturing the same
Publication Date: 2024.01.02 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11862469B2 patent drawing
  • US11862469B2 patent drawing
  • US11862469B2 patent drawing

AI summary

A method of forming a package structure includes the following steps. A first package structure is formed. The first package structure is connected to a second package structure. The method of forming the first package structure includes the following steps. A redistribution layer (RDL) structure is formed. A die is bonded to the RDL structure. The RDL structure is electrically connected to the die. A through via is formed on the RDL structure and laterally aside the die. An encapsulant is formed to laterally encapsulate the through via and the die. A protection layer is formed over the encapsulant and the die. A cap is formed on the through via and laterally aside the protection layer, wherein the cap has a top surface higher than a top surface of the encapsulant and lower than a top surface of the protection layer. The cap is removed from the first package structure.