Fan-Out Package Structure With Recessed Interposer for Dense PoP Stacking
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Solution Overview
Problem
The semiconductor industry faces manufacturing challenges in integrating multiple packages with different or similar functions using new packaging technologies like package on package (PoP), where traditional methods struggle with efficient bonding and packaging density.
Innovation Solution
A method for forming a chip package involves a carrier substrate with an interconnection structure, a semiconductor die bonded to the substrate, and an interposer substrate with a recess surrounding the die, along with a protective layer and conductive elements, allowing for efficient stacking and bonding with other package structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If package on package (PoP) technology is used to integrate multiple packages, then packaging density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the packaging structure into separate modules (first package, second package, interposer substrate) that can be manufactured independently and then stacked together. This segmentation allows each module to be optimized separately while achieving high overall packaging density through vertical integration.
Solution Approach 2:
The patent implements a nested structure where the interposer substrate is positioned within the recess of the first package, and the second package is stacked on top. This nested arrangement maximizes space utilization and achieves high packaging density while maintaining manufacturability through standardized bonding processes.
2Ease of manufacture
If traditional packaging methods are used, then manufacturing process is simpler, but packaging density decreases
Solution Approach 1:
The patent transitions from traditional lateral packaging arrangements to a vertical stacking configuration. By utilizing the vertical dimension with multiple packages stacked on top of each other through the interposer substrate, the design achieves higher packaging density while maintaining compatibility with existing manufacturing capabilities.
Solution Approach 2:
The interposer substrate serves as an intermediary element that facilitates bonding between the first and second packages. This mediator enables the PoP structure by providing a common bonding interface, thereby achieving high packaging density while keeping the manufacturing process manageable through standardized intermediate bonding steps.
3Quantity of substance
If multiple packages are integrated using PoP technology, then integration density is improved, but bonding process difficulty increases
Solution Approach 1:
The patent prepares the bonding surfaces in advance by forming recesses in the first package and positioning the interposer substrate before final stacking. This preliminary preparation ensures proper alignment and reduces bonding process complexity by pre-establishing the interfaces that will be joined.
Solution Approach 2:
The interposer substrate acts as a mediator that simplifies the bonding process between the first and second packages. By providing a standardized intermediate bonding interface, it reduces the overall bonding process difficulty while enabling high integration density through vertical stacking of multiple packages.
Data Source
AI summary
A package structure is provided. The package structure includes a redistribution structure and a semiconductor chip bonded to the redistribution structure. The package structure also includes an adhesive layer directly on the semiconductor chip. The redistribution structure is wider than the adhesive layer. The package structure further includes an interposer substrate bonded to the redistribution structure. A bottommost surface of the interposer substrate is spaced apart from a topmost surface of the redistribution structure.