Fan-Out Semiconductor Package With Recess Guide Pattern

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Solution Overview

Problem

Existing semiconductor package technologies, such as fan-in packages, face challenges in accommodating semiconductor chips with a large number of I/O terminals or compact sizes due to spatial limitations and the need for redistribution of I/O terminals, making it difficult to directly mount them on electronic device mainboards without using separate BGA substrates.

Innovation Solution

A fan-out semiconductor package design featuring a frame with a blind recess portion and a guide pattern that controls the profile of the recess portion's wall, allowing for redistribution of connection pads outwardly of the semiconductor chip, eliminating the need for a separate backside redistribution layer and enabling direct mounting on electronic device mainboards.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If a fan-in semiconductor package is used, then the semiconductor chip can be mounted, but the package size becomes large and additional BGA substrates are required for redistribution

Engineering Contradiction:
Improvepackage sizeVSAvoidstructure complexity
Core Design Contradiction:
Volume of moving objectVSDevice complexity

Solution Approach 1:

The patent transitions from a planar fan-in package structure to a three-dimensional fan-out package structure by forming a recess portion in the frame and disposing the semiconductor chip within it. This vertical dimensionality change allows connection pads to be redistributed outwardly on the front surface of the frame, eliminating the need for separate BGA substrates and reducing overall package size while maintaining electrical connectivity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The semiconductor chip is nested within the recess portion of the frame structure. The connection pads on the chip are electrically connected to redistribution layers that are embedded within the frame's recess portion, creating a nested configuration where the chip is housed inside the frame structure. This nesting eliminates the need for external BGA substrates and reduces package complexity.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Adaptability or versatility

If connection pads are redistributed outwardly of the semiconductor chip, then direct mounting on mainboards is enabled, but the frame structure becomes more complex

Engineering Contradiction:
Improvemounting flexibilityVSAvoidframe structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The frame structure is segmented into multiple functional layers including insulating layers, wiring layers, and connection via layers. The recess portion is divided into different regions with guide patterns and stopper layers to control the redistribution process. This segmentation allows for systematic organization of the complex redistribution function while maintaining manufacturability through standardized layer structures.

Inventive Principle:
Principle #1Segmentation

3Reliability

If a blind recess portion is formed in the frame, then the semiconductor chip can be securely disposed, but the manufacturing process becomes more complex

Engineering Contradiction:
Improvechip attachment reliabilityVSAvoidmanufacturing simplicity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The blind recess portion, guide patterns, and stopper layers are pre-formed in the frame structure before the semiconductor chip is mounted. This preliminary formation of the recess portion with controlled depth and profile ensures that the chip will be securely disposed and properly aligned during the subsequent mounting process, improving reliability while maintaining ease of manufacture through a sequential fabrication approach.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10347586B2Fan-out semiconductor package
Publication Date: 2019.07.09 SAMSUNG ELECTRONICS CO LTD
  • US10347586B2 patent drawing
  • US10347586B2 patent drawing
  • US10347586B2 patent drawing

AI summary

A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip having connection pads and disposed in the recess portion so that an inactive surface is disposed on the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; a connection member disposed on the frame and an active surface of the semiconductor chip and including a redistribution layer electrically connecting the wiring layers and the connection pads to each other; and a guide pattern disposed adjacent to a wall of the recess portion and disposed in the frame. An edge of the bottom surface of the recess portion has a groove portion.