Fan-Out Panel Package Structure for Step Difference Reliability
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Solution Overview
Problem
Existing semiconductor packages face challenges in miniaturization and multifunctionalization due to step differences between semiconductor chips and frame structures, leading to reliability issues and increased production costs.
Innovation Solution
The semiconductor package incorporates a redistribution structure with a tapered redistribution via that connects external connection terminals to fine-sized electrode pads, and a molding member that surrounds all surfaces of the semiconductor chip and frame structure, minimizing step differences and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional semiconductor package structure is used, then the package can be manufactured with existing processes, but step differences between the semiconductor chip and frame structure cause reliability issues
Solution Approach 1:
The patent introduces a redistribution structure with multiple layers arranged in different dimensions. The redistribution lines are arranged in a first direction while redistribution vias connect different layers in a second direction perpendicular to the first direction, creating a three-dimensional electrical connection network that resolves the step difference issue between chip and frame structure.
Solution Approach 2:
The redistribution structure is nested within the package structure, with redistribution lines and vias embedded in insulating layers between the chip and frame structure. The tapered redistribution vias are nested within the insulating layers, creating a compact multi-layer configuration that eliminates step differences while maintaining electrical connectivity.
2Volume of moving object
If fine-sized electrode pads are used for miniaturization, then the semiconductor chip can be miniaturized, but the connection between external terminals and fine pads becomes difficult
Solution Approach 1:
The patent uses multiple redistribution layers stacked in the vertical dimension to extend electrical connections from fine-sized electrode pads on the chip to external connection terminals on the frame structure. This multi-layer approach allows fine pads to connect to larger external terminals through intermediate redistribution layers, making the connection process more manageable.
Solution Approach 2:
The redistribution structure acts as an intermediary between the fine-sized electrode pads and external connection terminals. The redistribution lines and vias provide intermediate connection points that bridge the size and functional gap between the fine chip pads and larger external terminals, simplifying the manufacturing process.
3Productivity
If the semiconductor chip is mounted directly on the frame structure, then the manufacturing process is simple, but step differences cause reliability problems
Solution Approach 1:
The redistribution structure is prepared in advance as part of the package structure before the chip is mounted. The insulating layers and conductive patterns are formed on the frame structure beforehand, creating a pre-configured electrical network that will receive the chip connections and distribute signals to external terminals.
Solution Approach 2:
The redistribution structure serves as an intermediary layer between the chip and frame structure, allowing direct mounting of the chip while providing the necessary electrical redistribution function. This intermediary structure eliminates step difference reliability issues without requiring complex multi-step mounting processes.
4Device complexity
If external connection terminals are placed directly on the chip surface, then the package structure is simple, but fine-pitch connections are difficult to achieve
Solution Approach 1:
The patent moves external connection terminals from the chip surface to the frame structure, utilizing the vertical dimension and lateral space on the frame. The redistribution structure provides electrical connections through multiple layers, allowing fine-pitch connections on the chip to be mapped to larger-spaced external terminals on the frame structure.
Solution Approach 2:
The patent segments the electrical connection function into multiple components: electrode pads on the chip, redistribution lines and vias in intermediate layers, and external connection terminals on the frame structure. This segmentation allows each component to be optimized independently, achieving fine-pitch connections where needed while maintaining simpler external interfaces.
Data Source
AI summary
A semiconductor package includes a frame structure having a core portion and a lower pad under the core portion. A cavity penetrates the core portion, and a semiconductor chip is arranged in the cavity and has an active surface on which a bump pad is arranged and a non-active surface facing the active surface. A redistribution structure is positioned under the frame structure and the semiconductor chip, and is connected to the lower pad and the bump pad. A molding member covers the frame structure and the semiconductor chip and fills the cavity. The molding member surrounds a lower surface of the frame structure, the active surface of the semiconductor chip, the lower pad, and the bump pad.