Fan-Out Package Structure for Dense Die Routing
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Solution Overview
Problem
The semiconductor industry faces challenges in integrating smaller electronic components into smaller package areas, requiring more efficient packaging solutions to accommodate increased integration density and reduce space usage.
Innovation Solution
A package structure is formed using a carrier substrate with a release layer, where integrated circuit dies are adhered and encapsulated, followed by the formation of conductive features and redistribution structures to optimize spacing and connectivity, allowing for more efficient use of space and improved connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If integrated circuit dies are packaged in traditional configurations, then connectivity is achieved, but package area is excessive and integration density is limited
Solution Approach 1:
The patent implements fan-out wiring that extends conductive paths laterally beyond the die perimeter, utilizing the planar dimension to route signals around the die edges rather than directly through the die center. This dimensional approach allows multiple I/O connections to be established within a smaller package footprint by distributing routing paths across the package area, thereby reducing overall package size while maintaining high integration density
Solution Approach 2:
The package structure is divided into distinct functional regions including die attachment area, fan-out wiring regions, and encapsulation zones. The wiring is segmented into multiple layers and routing paths that can be independently optimized, allowing efficient space utilization and enabling higher integration density within reduced package dimensions
2Productivity
If component size is reduced to increase integration density, then more components fit in given area, but spacing between components becomes insufficient for proper routing
Solution Approach 1:
The fan-out wiring technique utilizes the lateral dimension by extending conductive traces beyond the die boundaries and routing them around the die perimeter. This approach effectively increases the available routing space without requiring increased spacing between adjacent dies, allowing tight component spacing while maintaining adequate signal routing paths through the expanded planar workspace
Solution Approach 2:
The patent implements multi-layer wiring structures where conductive paths are nested across different vertical levels. Lower layers handle certain routing functions while upper layers provide additional routing capacity, allowing sufficient spacing for signal integrity even when components are densely packed, as the nested layers effectively multiply the available routing real estate
Data Source
AI summary
An embodiment is a method including forming a first package. The forming the first package includes forming a through via adjacent a first die, at least laterally encapsulating the first die and the through via with an encapsulant, and forming a first redistribution structure over the first die, the through via, and the encapsulant. The forming the first redistribution structure including forming a first via on the through via, and forming a first metallization pattern on the first via, at least one sidewall of the first metallization pattern directly overlying the through via.