Fan-Out Package Singulation for High-Density I/O Redistribution
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Solution Overview
Problem
The increasing density of I/O pads on semiconductor dies due to miniaturization and functional integration complicates packaging, leading to yield reduction and waste in defective dies.
Innovation Solution
A method involving the formation of first and second trenches in a semiconductor wafer, with the first trench extending through the dielectric layer and the second trench penetrating through the passivation and interconnect structure, allows for efficient singulation and redistribution of I/O pads, enabling the creation of fan-out packages and discarding defective dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If I/O pad density is increased to accommodate more functions in smaller areas, then functional integration is improved, but packaging difficulty increases and yield decreases
Solution Approach 1:
The patent applies segmentation by dividing the wafer into multiple die regions separated by scribe lines, and further segmenting the dielectric layer to expose underlying structures. This allows individual die to be processed and packaged separately while maintaining the ability to handle high-density I/O pads through controlled separation and redistribution.
Solution Approach 2:
The patent utilizes dimensional transformation by forming trenches that extend through multiple layers (dielectric layer, passivation layer, interconnect structure) to create vertical separation. This multi-dimensional approach enables redistribution of I/O pads in both horizontal and vertical dimensions, facilitating packaging of high-density configurations.
2Reliability
If trench depth is increased to penetrate through passivation and interconnect structure, then delamination risk is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the first trench through the dielectric layer before forming the second trench that penetrates deeper structures. This sequential approach allows for controlled exposure of underlying layers and facilitates subsequent processing steps, reducing overall manufacturing complexity while achieving the reliability benefit of deep trench formation.
Solution Approach 2:
The patent implements local quality by creating trenches with different depths and characteristics in different regions of the wafer. The first trench extends through the dielectric layer while the second trench penetrates through passivation and interconnect structure, allowing localized structural modifications that enhance delamination resistance without uniformly increasing complexity across the entire device.
Data Source
AI summary
A package including a device die and an encapsulant is provided. The device die includes a semiconductor substrate, an interconnect structure, a conductive via, and a dielectric layer. The interconnect structure is disposed over the semiconductor substrate. The conductive via is disposed over and electrically coupled to the interconnect structure. The dielectric layer is disposed over the interconnect structure and laterally encapsulating the conductive via, wherein the dielectric layer includes a sidewall and a bottom surface facing the interconnect structure, and the sidewall of the dielectric layer is tilted with respect to the bottom surface of the dielectric layer. The encapsulant laterally encapsulates the device die.