Fan-Out Semiconductor Package Layout for Wider I/O Terminal Spacing
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Solution Overview
Problem
In highly-integrated semiconductor chips with a large number of input/output (I/O) terminals, the close proximity of terminals leads to interference issues, necessitating a solution to increase the distance between I/O terminals while maintaining compact and lightweight semiconductor packages.
Innovation Solution
A semiconductor package design featuring a lower redistribution structure with a conductive post having a concave top surface, integrated within a molding layer, which allows for increased spacing between I/O terminals and enhances reliability through a layered redistribution structure and molding configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a highly-integrated semiconductor chip with a large number of I/O terminals is used, then the data processing capability is improved, but the distance between I/O terminals decreases causing interference
Solution Approach 1:
The patent implements a fan-out wafer-level packaging structure where the semiconductor chip is mounted on a substrate and I/O terminals are redistributed to extended areas through multiple redistribution layers. This dimensional expansion allows maintaining high integration while increasing the effective distance between terminals by spreading them across a larger footprint area.
Solution Approach 2:
The patent introduces a substrate as an intermediary between the semiconductor chip and the external environment. The substrate provides a platform for mounting the chip and routing signals through redistribution patterns, effectively mediating the connection and allowing terminal spacing to be optimized separately from the chip's internal high-density layout.
2Reliability
If the distance between I/O terminals is increased to remove interference, then the reliability is improved, but the volume of the semiconductor package increases
Solution Approach 1:
The patent transitions from a traditional vertical stacking approach to a horizontal fan-out layout where I/O terminals are redistributed across an extended planar area on the substrate. This allows increasing the effective terminal spacing without proportionally increasing the overall package height, thus maintaining compactness while improving reliability.
Solution Approach 2:
The patent employs multiple redistribution layers nested within the substrate structure, where lower redistribution patterns are embedded in first insulating layers and upper redistribution patterns are embedded in second insulating layers. This nested arrangement allows complex signal routing and terminal spacing optimization within a compact vertical footprint.
3Object-affected harmful factors
If a fan-out semiconductor package structure is used to increase distance between I/O terminals, then the interference is reduced, but the device complexity increases
Solution Approach 1:
The patent divides the packaging structure into distinct functional segments: a substrate for mounting and signal routing, multiple insulating layers for electrical isolation, redistribution patterns for signal routing, and a molding layer for protection. This segmentation allows each component to be optimized independently while working together to reduce interference through increased terminal spacing.
Data Source
AI summary
A semiconductor package includes a semiconductor chip including a chip pad; a lower redistribution structure on the semiconductor chip, the lower redistribution structure including a lower redistribution insulating layer and a lower redistribution pattern electrically connected to the chip pad of the semiconductor chip; a molding layer on at least a portion of the semiconductor chip; and a conductive post in the molding layer, the conductive post having a bottom surface and a top surface, the bottom surface of the conductive post being in contact with the lower redistribution pattern of the lower redistribution structure and the top surface of the conductive post having a concave shape.