Fan-Out Semiconductor Package With Stacked Chips and Shorter Signal Paths
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor packages face challenges in increasing the number of external connection terminals while maintaining a small planar area, which is necessary for improved performance, and reducing manufacturing costs by minimizing the chip size.
Innovation Solution
A fan-out semiconductor package design that includes a wiring substrate with specific fan-in and fan-out regions, redistribution structures, and stacked chip configurations, utilizing a Ti-Cu alloy seed layer and redistribution vias to enhance integration capacity and reduce signal connection length between chip structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the planar area of the semiconductor package is increased to increase the number of external connection terminals, then the number of external connection terminals is improved, but the planar area of the semiconductor chip increases leading to increased manufacturing cost
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked configuration by placing multiple semiconductor chips (first chip, second chip, third chip) vertically on the substrate. This vertical stacking enables increased integration capacity and more external connection terminals without proportionally increasing the planar area of individual chips, thereby resolving the contradiction between terminal quantity and chip area.
Solution Approach 2:
The patent implements a nested structure where multiple chips are stacked and interconnected through through-substrate vias and redistribution layers. The first chip, second chip, and third chip are nested vertically with their respective wiring structures and connection terminals integrated within the same vertical space, allowing high-density terminal integration without proportional area increase.
2Ease of manufacture
If the planar area of the semiconductor chip is reduced to decrease manufacturing cost, then the manufacturing cost is improved, but the planar area of the semiconductor package decreases limiting the number of external connection terminals
Solution Approach 1:
By utilizing the vertical dimension through stacked chip configuration and through-substrate vias, the patent achieves high terminal count with small individual chip areas. The redistribution layers and vertical interconnections enable efficient space utilization that allows cost-effective small chips to provide numerous external terminals.
Solution Approach 2:
The substrate serves multiple functions: it provides mechanical support, electrical interconnection between stacked chips, and housing for external connection terminals. The through-substrate vias and redistribution layers enable the substrate to act as both a carrier and an interconnection network, allowing small chips to achieve high terminal density through efficient multi-functional integration.
3Productivity
If multiple semiconductor chips are stacked to increase integration capacity, then the integration capacity is improved, but the signal connection length between chip structures increases
Solution Approach 1:
The patent introduces redistribution layers and through-substrate vias as intermediary structures that provide direct vertical electrical pathways between stacked chips. These intermediaries enable short signal connections between the first chip, second chip, and third chip, preventing signal path length from increasing proportionally with integration capacity.
Data Source
AI summary
A fan-out semiconductor package includes a wiring substrate including a first fan-in region, a fan-out region surrounding the first fan-in region, and a second fan-in region, a first fan-in chip structure, a second fan-in chip structure, a first redistribution structure including first redistribution elements disposed on a bottom surface of the wiring substrate, and a second redistribution structure disposed on a top surface of the wiring substrate, and a chip wiring structure formed on a top surface of the second chip, and the second redistribution structure includes a second redistribution layer extending to the first fan-in region and the fan-out region, a plurality of second redistribution vias integrally formed with the second redistribution layer and extending downward, and a seed layer surrounding the second redistribution layer and bottom surfaces of the plurality of second redistribution vias.