Fan-Out Package With Mechanical Support Layer And TEVs
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Solution Overview
Problem
Current semiconductor device packaging methods, such as through silicon vias (TSVs) and through hole vias (THVs), are time-consuming, costly, and prone to defects due to void formation, and redistribution layers (RDLs) provide limited mechanical strength and reliability in 3-D fan-out wafer-level chip-scale packages (FO-WLCSPs).
Innovation Solution
A method involving the formation of a robust fan-out package with vertical interconnects and a mechanical support layer, where a semiconductor die is encapsulated, an interconnect structure with conductive bumps is formed, and a through encapsulant via (TEV) is created to connect the interconnect structure, enhancing electrical connectivity and mechanical support.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through silicon vias (TSVs) and through hole vias (THVs) are used for vertical interconnection, then electrical connectivity is achieved, but manufacturing time increases and production cost increases
Solution Approach 1:
The patent applies preliminary action by forming the mechanical support layer before creating the vertical interconnect structures. This pre-established support structure enables subsequent via formation processes to proceed more efficiently without requiring complex sidewall passivation steps, thereby reducing manufacturing time while maintaining reliable electrical connectivity.
Solution Approach 2:
The patent extracts and eliminates the electroplating process entirely from the manufacturing flow. By using alternative via filling methods such as electroless plating or direct deposition, the time-consuming electroplating step is removed, significantly reducing production time while still achieving the necessary electrical connectivity through the vertical interconnects.
2Reliability
If through silicon vias (TSVs) and through hole vias (THVs) are used for vertical interconnection, then electrical connectivity is achieved, but manufacturing cost increases
Solution Approach 1:
The patent removes the electroplating process from the manufacturing sequence, eliminating the need for plating baths, electroplating equipment, and associated materials. This extraction of the costly electroplating step directly reduces manufacturing costs while alternative via filling methods maintain the electrical connectivity function.
Solution Approach 2:
The patent employs simpler, less expensive via formation methods that do not require expensive electroplating infrastructure. By using electroless plating or direct material deposition, the manufacturing process relies on more cost-effective techniques that reduce equipment investment and operational expenses while achieving the same electrical interconnection function.
3Reliability
If through silicon vias (TSVs) and through hole vias (THVs) are used for vertical interconnection, then electrical connectivity is achieved, but defect rate increases due to void formation
Solution Approach 1:
By eliminating the electroplating process, the patent removes the primary source of void formation that occurs during copper deposition. The alternative via filling methods used in this patent inherently produce more uniform material distribution without the voids that plague electroplated structures, thereby reducing defect rates while maintaining electrical connectivity.
4Reliability
If redistribution layers (RDLs) are used in 3-D fan-out packages, then electrical interconnection is provided, but mechanical strength is limited
Solution Approach 1:
The patent employs composite materials by integrating a mechanical support layer made from structurally robust materials into the package architecture. This support layer, positioned beneath the redistribution layers, provides the mechanical strength needed to support the thin RDL structures while allowing the RDLs to maintain their electrical interconnection function without compromising overall package strength.
Solution Approach 2:
The patent segments the package structure into distinct functional layers: a mechanical support layer for structural integrity and redistribution layers for electrical interconnection. This segmentation allows each layer to be optimized for its specific function, with the support layer providing strength and the RDLs providing electrical connectivity without相互 compromise.
5Ease of manufacture
If conventional packaging methods are used, then semiconductor devices are packaged, but warpage control is difficult
Solution Approach 1:
The patent uses composite material structures with the mechanical support layer having controlled mechanical properties that compensate for thermal expansion mismatches between different package components. This composite construction inherently reduces warpage by balancing stresses across the package structure during temperature cycling, while maintaining ease of manufacturing through a standardized layering process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing time and costs, improves reliability by minimizing defects and warpage, and provides enhanced mechanical strength for 3-D interconnects, enabling more efficient production of smaller, higher-density semiconductor devices.
Implementation Method 1
depositing an encapsulant around the semiconductor die
Implementation Method 2
depositing conductive material within the opening to form a conductive through encapsulant via
Data Source
AI summary
A semiconductor device has a semiconductor die. An encapsulant is deposited around the semiconductor die. An interconnect structure having a conductive bump is formed over the encapsulant and semiconductor die. A mechanical support layer is formed over the interconnect structure and around the conductive bump. The mechanical support layer is formed over a corner of the semiconductor die and over a corner of the interconnect structure. An opening is formed through the encapsulant that extends to the interconnect structure. A conductive material is deposited within the opening to form a conductive through encapsulant via (TEV) that is electrically connected to the interconnect structure. A semiconductor device is mounted to the TEV and over the semiconductor die to form a package-on-package (PoP) device. A warpage balance layer is formed over the encapsulant opposite the interconnect structure.