Fan-Out Package Structure With Thermal Paths for PoP Heat Dissipation
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving efficient heat dissipation in compact integrated fan-out packages and package-on-package (PoP) structures, which are essential for maintaining performance in densely integrated electronic components.
Innovation Solution
The implementation of a package structure that includes a semiconductor die laterally encapsulated by an insulating encapsulation, a redistribution circuit structure with thermal enhancement structures thermally coupled to the semiconductor die, a backside dielectric layer with conductive terminals, an electronic device stacked over the redistribution circuit structure, and an underfill thermally coupled to the thermal enhancement structures, which enhances heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If integrated fan-out packages and PoP structures are made compact to increase integration density, then the area occupied by components is reduced, but heat dissipation performance deteriorates
Solution Approach 1:
The patent introduces thermal enhancement structures that extend in the vertical dimension (through vias penetrating the substrate) rather than only horizontal expansion. This allows heat dissipation pathways to develop in the Z-direction, enabling effective thermal management in compact footprints by utilizing the third dimension for heat extraction.
Solution Approach 2:
The thermal enhancement structures are divided into multiple segments including through vias, thermal pads, and heat sinks distributed across the substrate. This segmentation creates multiple parallel heat dissipation pathways, allowing heat to be conducted through various routes simultaneously, thereby improving overall heat dissipation efficiency in compact packages.
2Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but heat dissipation challenges increase
Solution Approach 1:
As integration density increases with smaller features, the patent compensates by developing vertical heat dissipation pathways through the substrate thickness. The through vias and thermal pads extend heat conduction in the vertical dimension, allowing high-density horizontal integration without compromising thermal performance.
Solution Approach 2:
The thermal enhancement structures act as intermediary elements between the densely integrated components and the heat sink. These structures (through vias, thermal pads) serve as thermal conduits that bridge the heat generation points in high-density circuits to the external heat dissipation mechanisms, enabling effective thermal management despite reduced feature sizes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively enhances heat dissipation performance in compact integrated fan-out packages and PoP structures, addressing the challenge of maintaining performance in densely integrated electronic components.
Implementation Method 1
an underfill disposed between the backside dielectric layer and the electronic device, wherein the underfill is thermally coupled to the thermal enhancement structures
Implementation Method 2
a redistribution circuit structure with thermal enhancement structures thermally coupled to the semiconductor die
Implementation Method 3
conductive terminals penetrating through the backside dielectric layer
Data Source
AI summary
A package structure including a semiconductor die, a redistribution circuit structure, a backside dielectric layer, conductive terminals, an electronic device, and an underfill is provided. The semiconductor die laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes redistribution conductive layers and thermal enhancement structures electrically insulated from the redistribution conductive layers, and the thermal enhancement structures are thermally coupled to the semiconductor die. The backside dielectric layer is disposed on the redistribution circuit structure. The conductive terminals penetrate through the backside dielectric layer. The electronic device is disposed over the backside dielectric layer and electrically connected to the redistribution circuit structure through the conductive terminals. The underfill is disposed between the backside dielectric layer and the electronic device, wherein the underfill is thermally coupled to the thermal enhancement structures.