Integrated Fan-Out Package Thickness Leveling

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Solution Overview

Problem

Integrated fan-out packages face reliability issues due to thickness differences between chips, which affect the yield rate of fabrication, as the electrical connection between chips and the redistribution circuit structure on the molding compound deteriorates.

Innovation Solution

A thickness leveling process is implemented, where insulating material is ground to ensure uniform thickness of integrated circuits, followed by de-bonding, dielectric material formation, and singulation to create chip modules with consistent thickness, which are then embedded in a second insulating encapsulation alongside a redistribution circuit structure for stable electrical connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If multiple chips with different thicknesses are encapsulated in integrated fan-out packages, then compact packaging is achieved, but electrical connection reliability deteriorates due to thickness differences

Engineering Contradiction:
Improvepackage compactnessVSAvoidelectrical connection reliability
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The patent applies preliminary action by performing thickness leveling on chips before encapsulation. The grinding process removes excess material from thicker chips to match the thickness of thinner chips, ensuring uniform thickness across all chips before they are embedded in the molding compound. This preliminary thickness uniformity prevents connection reliability deterioration that would otherwise occur due to thickness variations.

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If chips of varying thicknesses are used in integrated fan-out packages, then manufacturing flexibility is improved, but fabrication yield rate decreases due to connection deterioration

Engineering Contradiction:
Improvemanufacturing flexibilityVSAvoidfabrication yield rate
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The thickness leveling process is performed as a preliminary step before chip assembly and encapsulation. By grinding chips to uniform thickness beforehand, the patent enables flexible mixing of chips from different manufacturing batches or processes while ensuring that all chips will have compatible thicknesses for reliable electrical connections, thereby maintaining high fabrication yield rates.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This process minimizes thickness variation, enhancing the reliability and yield rate of integrated fan-out packages by ensuring consistent electrical connections and compact, reliable packaging.

Implementation Method 1

the insulating material and the integrated circuits are ground until the rear surfaces of the integrated circuits are exposed

Methodology Applied
Scientific EffectGrinding: Abrasion

Data Source

PatentUS9824902B1Integrated fan-out package and method of fabricating the same
Publication Date: 2017.11.21 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9824902B1 patent drawing
  • US9824902B1 patent drawing
  • US9824902B1 patent drawing

AI summary

An integrated fan-out package including a chip module, a second integrated circuit, a second insulating encapsulation, and a redistribution circuit structure is provided. The chip module includes a first insulating encapsulation and a first integrated circuit embedded in the first insulating encapsulation, and the first integrated circuit includes a first surface and first conductive terminals on the first surface. The second integrated circuit includes a second surface and second conductive terminals on the second surface. The chip module and the second integrated circuit are embedded in the second insulating encapsulation. The first and second conductive terminals are accessibly exposed from the first and second insulating encapsulation. The redistribution circuit structure covers the first surface, the second surfaces, the first insulating encapsulation, and the second insulating encapsulation. The redistribution circuit structure is electrically connected to the first and second conductive terminals. Methods of fabricating the integrated fan-out package are also provided.