Fan-Out Semiconductor Package With Variable Signal Line Width
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Solution Overview
Problem
In fan-out semiconductor packages, the signal patterns passing over degassing holes in ground patterns are prone to breakage due to surface steps, leading to reduced adhesion between the insulating layer and dry film resist, which can result in defects like short-circuits.
Innovation Solution
The fan-out semiconductor package design includes a second redistribution layer with a signal pattern that has a wider line portion overlapping the degassing holes, which increases the reliability of the signal pattern and prevents breakage, and optionally features a metal portion within the degassing holes to reinforce the structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a degas design with circular or linear shape is implemented in ground patterns to improve adhesion and allow degas discharge, then close adhesion between insulating layer and copper foil is improved, but an insulating layer dent phenomenon occurs and surface steps are formed
Solution Approach 1:
The patent applies local quality by making the signal pattern width variable rather than uniform. Specifically, the signal pattern is designed with a first width in regions away from degas holes and a second, greater width when passing over degas holes. This localized modification addresses the surface step problem only where needed (over degas holes) while maintaining standard design elsewhere, thus improving reliability without unnecessarily complicating the entire structure.
2Object-generated harmful factors
If the insulating layer surface has steps due to degassing holes, then degas discharge is improved, but patterns on the insulating layer are broken and adhesion with dry film resist is reduced
Solution Approach 1:
The patent applies local quality by making the signal pattern width variable rather than uniform. Specifically, the signal pattern is designed with a first width in regions away from degas holes and a second, greater width when passing over degas holes. This localized modification addresses the surface step problem only where needed (over degas holes) while maintaining standard design elsewhere, thus improving reliability without unnecessarily complicating the entire structure.
3Object-generated harmful factors
If plating solution permeates into the insulating layer and dry film resist due to surface steps, then degas discharge is facilitated, but short-circuit defects occur
Solution Approach 1:
The patent applies local quality by making the signal pattern width variable rather than uniform. Specifically, the signal pattern is designed with a first width in regions away from degas holes and a second, greater width when passing over degas holes. This localized modification addresses the surface step problem only where needed (over degas holes) while maintaining standard design elsewhere, thus improving reliability without unnecessarily complicating the entire structure.
Data Source
AI summary
A fan-out semiconductor package includes: a semiconductor chip; an encapsulant encapsulating at least portions of the semiconductor chip; and a first connection member disposed on the semiconductor chip and including a first redistribution layer electrically connected to the connection pads and a second redistribution layer electrically connected to the connection pads and disposed on the first redistribution layer. The first redistribution layer includes a first pattern having a plurality of degassing holes, the second redistribution layer includes a second pattern having a first line portion having a first line width and a second line portion connected to the first line portion and having a second line width greater than the first line width, and the second line portion overlaps at least one of the plurality of degassing holes when being projected in a direction perpendicular to the active surface.