Fan-Out Multichip Packaging Without Organic Substrate Warpage
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Solution Overview
Problem
Existing semiconductor packages using organic substrates face issues such as strip warpage, micro-bump misalignment, large package warpage, and slow manufacturing speeds due to CTE mismatch, leading to increased package size and defects, which hinder high-volume manufacturing and integration.
Innovation Solution
Implementing fan-out packaging (FOP) technology at the wafer and panel level, eliminating the organic substrate, and using a redistribution layer-first approach with two compression molding processes to encapsulate controllers and memory dies, along with a moldable underfill and dielectric layers to reduce thermal interaction and warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If organic substrate is used in semiconductor packages, then electrical connection and component support are achieved, but strip warpage, micro-bump misalignment, and large package warpage occur due to CTE mismatch
Solution Approach 1:
The patent removes the organic substrate from the package structure entirely, replacing it with a substrateless design where semiconductor dies are directly bonded to each other through micro-bumps. This extraction eliminates the CTE mismatch between organic substrate and silicon dies, thereby preventing strip warpage and micro-bump misalignment while improving manufacturing precision and reliability
Solution Approach 2:
The patent merges multiple semiconductor dies directly together through micro-bump bonding without an intermediate organic substrate. This direct bonding approach combines the functional layers (signal layer, power layer, ground layer) into a compact stacked structure, eliminating the need for organic substrate support and resolving the CTE mismatch issue that caused warpage and alignment defects
2Ease of manufacture
If organic substrate is used for component mounting, then electrical connection is established, but manufacturing speed decreases due to handling difficulties
Solution Approach 1:
By removing the organic substrate, the patent eliminates the handling and processing steps associated with substrate mounting and alignment. The substrateless design allows for direct die-to-die bonding, simplifying the manufacturing process and increasing production speed while maintaining ease of manufacture through standardized micro-bump bonding techniques
3Temperature
If components are mounted far from each other to reduce thermal interaction, then thermal performance improves, but package size increases
Solution Approach 1:
The patent transitions from a planar layout where components must be spaced apart to a three-dimensional stacked architecture. Multiple semiconductor dies are vertically stacked and bonded through micro-bumps, allowing thermal management through vertical separation while maintaining a compact horizontal footprint. This dimensional change enables reduced package size while still managing thermal interaction through the substrateless design and direct bonding interfaces
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced package height and cost, improved manufacturing throughput, and enhanced thermal performance by eliminating organic substrate-related defects, while allowing for finer line/space parameters and better solder joint reliability.
Implementation Method 1
forming a first mold layer by compressing a first mold compound on the plurality of controllers and the first set of one or more redistribution layers such that the first mold compound surrounds the plurality of controllers
Implementation Method 2
forming a second mold layer by compressing a second mold compound on the plurality of semiconductor dies and the second set of one or more redistribution layers such that the second mold compound surrounds the plurality of semiconductor dies
Implementation Method 3
a moldable underfill and dielectric layers to reduce thermal interaction and warpage
Data Source
AI summary
Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a controller, a first mold compound surrounding the controller, a plurality of semiconductor dies, a second mold compound surrounding the plurality of semiconductor dies, and one or more through-mold interconnects electrically coupling the controller to the plurality of semiconductor dies.