Fan-Out Packaging With Embedded Copper Pillars
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Solution Overview
Problem
Conventional two-dimensional integrated circuit packaging techniques face limitations in density and complexity due to physical constraints, leading to increased circuit RC delay and power consumption, and hybrid coupling methods in Package on Package (PoP) affect the characteristics of packaged dies/packages.
Innovation Solution
A method for forming a packaged device substrate with embedded Cu pillars that allows for the stacking and electrical coupling of fan-out structures, using a hybrid-bonding technique to connect dielectric and conductive materials, enhancing electrical connections and reducing AC impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional integrated circuit packaging is used, then manufacturing simplicity is maintained, but packaging density is limited
Solution Approach 1:
The patent transitions from two-dimensional packaging to three-dimensional fan-out packaging structure, where multiple device substrates are stacked vertically and connected through conductive pillars extending through dielectric layers. This dimensional change enables higher packaging density by utilizing vertical space rather than only horizontal plane.
Solution Approach 2:
The patent implements a nested structure where conductive pillars are embedded within dielectric layers, which in turn encapsulate device substrates. Multiple layers are nested vertically, with each layer containing substrates and interconnection structures, creating a compact three-dimensional integrated packaging architecture.
2Quantity of substance
If the number of devices is increased in one chip, then integration density is improved, but circuit RC delay and power consumption increase
Solution Approach 1:
By stacking device substrates vertically in three dimensions and connecting them through conductive pillars, the patent reduces the horizontal interconnection distance between devices. This shortens signal transmission paths and reduces RC delay, thereby lowering power consumption while achieving higher integration density.
3Quantity of substance
If hybrid coupling method is used in Package on Package, then stacking of dies is enabled, but electrical performance and stiffness are adversely affected
Solution Approach 1:
The patent employs uniform conductive pillars made of the same material composition throughout the stacked structure, replacing the hybrid coupling method that combines different bonding techniques. This homogeneous approach ensures consistent electrical properties and mechanical stiffness across all interconnections between stacked device substrates.
Data Source
AI summary
The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.