3D Fan-Out Wafer Packaging With Embedded Passives and TMVs
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in minimizing package thickness and volume while efficiently integrating and accessing passive components, leading to increased parasitic resistance and inductance, and limited integration of discrete passive components.
Innovation Solution
The method involves constructing three-dimensional fan-out wafer-level packages that embed discrete passive surface-mount-technology (SMT) components within the molding area of the bottom package, allowing direct access by the top package solder balls, and using Through-Mold/Encapsulation-Vias to connect these components to both top and bottom dies, thereby reducing parasitic effects and optimizing electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If discrete passive components are integrated within the molding area of wafer-level packages, then PCB area and volume occupation is minimized, but parasitic resistance and inductance increase
Solution Approach 1:
The patent transitions from planar PCB mounting to three-dimensional package stacking, moving passive components from the PCB surface to the internal volume of the package. Multiple dies and passive components are stacked vertically, utilizing the Z-dimension to achieve miniaturization while maintaining electrical performance through optimized vertical interconnects
Solution Approach 2:
The patent embeds discrete passive components within the molding compound volume, nesting them between stacked dies. The passive components are positioned in the spaces between functional dies, effectively utilizing the package volume and reducing the overall footprint while maintaining electrical performance
2Length of stationary object
If package substrate thickness is minimized using thinner conductive and dielectric layers, then package thickness is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent merges the package substrate with the molding compound by eliminating the traditional separate substrate structure. The molding compound serves dual functions as both encapsulation material and interconnection medium, containing embedded passive components and providing electrical interconnects through Through-Mold-Vias, thereby reducing overall package thickness while simplifying the layer structure
Solution Approach 2:
The patent changes the fundamental parameters of the package structure by transitioning from a multi-layer substrate architecture to a thin molding compound-based structure. The molding compound thickness is optimized to provide sufficient mechanical support and electrical isolation while minimizing overall package height, and Through-Mold-Vias replace traditional substrate vias to achieve shorter interconnect lengths
3Productivity
If Through-Mold-Vias are used to enable package stacking, then integration of multiple dies is achieved, but parasitic inductance increases
Solution Approach 1:
The patent performs preliminary actions by pre-positioning passive components within the molding compound before die stacking, and by pre-establishing Through-Mold-Via interconnects during the molding process. This allows optimization of the electrical interconnect paths before final package assembly, enabling shorter current loops and reduced parasitic inductance through careful placement and routing design
Solution Approach 2:
The patent applies local quality optimization by varying the distribution and configuration of Through-Mold-Vias based on local electrical performance requirements. Different regions of the package utilize different Via densities and routing patterns to minimize parasitic inductance in high-frequency signal paths while maintaining robust power delivery in power distribution regions
Data Source
AI summary
In accordance with disclosed embodiments, there is a method of integrating and accessing passive components in three-dimensional fan-out wafer-level packages. One example is a microelectronic die package that includes a die, a package substrate attached to the die on one side of the die and configured to be connected to a system board, a plurality of passive devices over a second side of the die, and a plurality of passive device contacts over a respective passive die, the contacts being configured to be coupled to a second die mounted over the passive devices and over the second side of the die.