Fan-Out High-Density Packaging Method for System Integration
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Solution Overview
Problem
Current fan-out wafer level packaging methods are limited in achieving high-density, multi-layer packaging structures with complex connections and system-level integration, as they primarily support single chip functions and lack the integration needed for advanced electronic systems.
Innovation Solution
A fan-out high-density packaging method involving a packaging substrate with a stripping film, protection layers, and a metal redistribution layer, along with sequential formation of mounting, sealant, and wiring layers, allowing for the connection of multiple chips and passive devices, and the use of solder balls for electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional fan-out wafer level packaging methods are used, then single chip function is supported, but system-level packaging integration degree remains undesired
Solution Approach 1:
The patent implements multi-layer packaging structures where package layers are stacked and interconnected through vias and conductive structures. Each layer contains mounting layers, sealant layers, and wiring layers that are nested within the overall package structure, enabling system-level integration by embedding multiple functional layers like a nested doll configuration
Solution Approach 2:
The patent transitions from planar single-layer packaging to three-dimensional multi-layer packaging by stacking multiple package layers vertically. This dimensional change allows complex system-level integration by utilizing the vertical dimension for interlayer connections through vias and conductive structures, thereby increasing integration density without expanding the horizontal footprint
2Device complexity
If traditional packaging methods are used, then manufacturing process is simple, but multi-layer packaging structures with complex connections cannot be manufactured
Solution Approach 1:
The patent employs photolithography pattern openings formed in advance on protection layers to define via locations and conductive structure positions before subsequent manufacturing steps. This preliminary patterning action enables precise placement of complex multi-layer connections while maintaining manufacturing efficiency through standardized photolithography processes
Solution Approach 2:
The patent divides the packaging structure into discrete functional layers including mounting layers, sealant layers, and wiring layers, each with specific functions. This segmentation allows independent fabrication and optimization of each layer type while maintaining overall system integration through standardized interlayer connections, thereby enabling complex multi-layer structures with manageable manufacturing complexity
3Adaptability or versatility
If peripheral circuits are added outside the final products, then complete system functions are achieved, but packaging integration density decreases
Solution Approach 1:
The patent merges passive devices (capacitors, inductors, resistors) and active chips into a single integrated package structure through the multi-layer packaging system. These components are mounted on the same substrate and interconnected through vias and conductive structures within the package, eliminating the need for external peripheral circuits and thereby maximizing packaging integration density while achieving complete system functions
Data Source
AI summary
A fan-out high-density packaging method includes providing a packaging substrate, forming a stripping film on the packaging substrate, and forming a first protection layer on the stripping film and pre-designed photolithography pattern openings on the first protection layer. The method also includes forming a metal redistribution layer on the surface of the first protection layer and in the photolithography pattern openings, forming a second protection layer on the first protection layer and partially exposing the metal redistribution layer, and forming at least one package layer on the second protection layer. Each of at least one package layer includes a straight mounting layer, a sealant layer, and a wiring layer formed in sequence, and the package layer connects the metal redistribution layer through the wiring layer. Further, the method includes forming at least one top-level package layer on top of the at least one package layer, removing the packaging substrate and the stripping film to expose the metal redistribution layer in the first protection layer, and planting metal solder balls on the exposed metal redistribution layer.