Wafer system-level fan-out packaging structure and manufacturing method
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Solution Overview
Problem
Current fan-out packaging technologies face challenges with large package area and thickness, complex procedures, and low reliability, which hinder the integration of high-density chips for miniaturization and low power consumption in semiconductor packaging.
Innovation Solution
A wafer system-level fan-out packaging structure and manufacturing method involving a redistribution layer with a plastic packaging layer that covers a die and patch element, utilizing a carrier substrate and release layer for precise bonding and packaging, along with under-bump-metallization and solder bumps for enhanced connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fan-out packaging technology is used for integrated multi-chip packaging, then chip integration and functionality are improved, but package area and thickness increase
Solution Approach 1:
The patent transitions from planar packaging to three-dimensional vertical stacking by introducing multiple carrier substrates stacked in the vertical direction. Carrier substrates are bonded together with chips mounted on each carrier, enabling space utilization in the vertical dimension rather than only horizontal expansion. This dimensional transition allows higher integration density while controlling package footprint area.
Solution Approach 2:
The patent implements a nested structure where multiple carrier substrates are stacked and bonded together in a tiered configuration. Each carrier substrate contains chips and routing layers, and carriers are nested vertically with connection channels passing through intermediate carriers. This nesting approach consolidates multiple chip functions into a compact stacked architecture, reducing overall package area while maintaining high integration.
2Adaptability or versatility
If fan-out packaging technology is used for integrated multi-chip packaging, then chip integration is improved, but package thickness increases
Solution Approach 1:
The patent divides the integrated system into multiple discrete carrier substrates, each containing a subset of chips and their associated routing. This segmentation allows the thick integrated structure to be broken into thinner modular layers that are stacked and connected. Each carrier substrate has controlled thickness, and the overall package thickness is managed by optimizing the number and arrangement of these segmented carriers rather than creating one monolithic thick package.
Solution Approach 2:
By stacking carrier substrates vertically and utilizing horizontal routing channels within each carrier, the patent redistributes the integration volume across multiple dimensions. This reduces the vertical thickness requirement by utilizing horizontal space for signal routing and interconnections, allowing high integration without proportionally increasing package thickness.
3Manufacturing precision
If through-silicon-via technology or silicon interposers are used, then ultra-small pins are effectively connected, but manufacturing cost increases significantly
Solution Approach 1:
The patent replaces expensive silicon interposer materials with organic substrate materials for carrier substrates. These organic carriers serve the temporary function of mounting and routing during the packaging process, then can be removed or left as part of the final package. This substitution dramatically reduces material cost while maintaining the required precision for ultra-small pin connections through careful design of routing channels and bonding interfaces.
Solution Approach 2:
The patent introduces carrier substrates as intermediary elements between chips and the final package substrate. These carriers provide the necessary precision alignment and routing functionality during assembly, then can be selectively removed or integrated. The carrier acts as a temporary mediator that enables precise pin connections without requiring expensive silicon interposers, reducing overall manufacturing cost while maintaining connection quality.
4Adaptability or versatility
If existing SIP technology is used to integrate multiple functional chips, then functionality and efficiency are improved, but package volume increases
Solution Approach 1:
The patent transitions from horizontal planar arrangement of multiple functional chips to vertical stacking of carrier substrates. Each carrier contains functional chips and routing, and carriers are stacked with interconnections passing through vertical channels. This vertical integration consolidates what would otherwise require large horizontal space into a compact three-dimensional structure, dramatically reducing package volume while maintaining or enhancing total functionality through higher integration density.
Data Source
AI summary
A wafer system-level fan-out packaging structure and a manufacturing method. The method includes: forming a redistribution layer, where the redistribution layer includes a first surface and an opposite second surface; providing a patch element, and bonding the patch element to the second surface; providing a die having a bump disposed on a front side, and bonding the front side of the die to the second surface of the redistribution layer through the bump; and forming a plastic packaging layer on the second surface of the redistribution layer, where the plastic packaging layer covers the patch element, back side and side surfaces of the die. In the wafer system-level fan-out packaging structure and the manufacturing method of the present disclosure, the die and the patch element are packaged in a plastic packaging layer, and the die and the patch element are connected and let out by the redistribution layer.