Wafer Ring Support for Fan-Out Packaging Stability
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Solution Overview
Problem
Integrated Fan-Out Wafer-Level Packaging (InFO-WLP) and chip-on-wafer-on-substrate (CoWoS) techniques face mechanical instability due to thermal expansion mismatch and require temporary bonding, which increases costs and manufacturing time.
Innovation Solution
A method is developed to form a ring portion as a handle to support the thin wafer, minimizing adhesive use and avoiding temporary bonding, while the coefficient of thermal expansion differences are mitigated by not using molding techniques. This involves forming conductive vias, grinding the wafer to create an inner and ring portion, and etching to expose the via ends, allowing for electrical connections and handling without adhesives.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If temporary bonding techniques are used to handle thin wafers, then the wafer can be supported during processing, but additional residue adhesives and extra cost and manufacturing time are introduced
Solution Approach 1:
The wafer is segmented into an inner portion and a ring portion through selective grinding, allowing the ring portion to serve as a structural support that eliminates the need for temporary bonding techniques while enabling independent handling of the inner portion
Solution Approach 2:
The ring portion of the wafer itself serves as the support structure during processing, eliminating the need for external adhesives or temporary bonding materials. The wafer supports itself through its own structural modification
2Strength
If molding techniques are used to package the semiconductor device, then mechanical protection is provided, but coefficient of thermal expansion (CTE) difference mismatching causes mechanical instability
Solution Approach 1:
The molding technique is extracted/removed from the process entirely. Instead of using a separate molding material that would cause CTE mismatch, the invention uses the wafer's own ring portion as both the structural support and the protective element, eliminating the source of thermal expansion problems
Solution Approach 2:
The ring portion and inner portion are both made of the same wafer material (silicon), ensuring homogeneous thermal expansion characteristics throughout the structure, eliminating CTE mismatch issues that would arise from using different molding materials
3Difficulty of detecting and measuring
If the entire wafer is ground down to expose conductive vias, then all via ends are exposed, but the wafer loses structural support and becomes too thin to handle
Solution Approach 1:
The wafer is segmented into an inner portion and a ring portion through selective grinding. The ring portion retains full thickness for structural support while the inner portion is ground down to expose conductive via ends, allowing simultaneous via exposure and structural integrity
Solution Approach 2:
Different regions of the wafer are given different qualities: the ring portion maintains full thickness for structural support and handling, while the inner portion is ground down to expose via ends for electrical connections, with each region optimized for its specific function
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively supports thin wafers during fabrication, reduces adhesive usage, and minimizes the impact of thermal expansion mismatches, thereby enhancing mechanical stability and reducing manufacturing time and costs.
Implementation Method 1
grinding the second surface of the wafer to form an inner portion and a ring portion surrounding the inner portion of the wafer
Implementation Method 2
etching the inner portion to expose the second end of the conductive via
Data Source
AI summary
A method for fabricating a semiconductor package, the method includes forming at least one conductive via having a first end and a second end opposite the first end in a wafer, in which the wafer has a first surface and a second surface opposite the first surface, and the first end of the at least one conductive via is exposed of the first surface of the wafer; grinding the second surface of the wafer to form an inner portion and a ring portion surrounding the inner portion of the wafer, wherein the inner portion has a thinner thickness than that of the ring portion; and etching the inner portion to expose the second end of the at least one conductive via.