Fan-Out Semiconductor Packaging Without Laser-Drilled Through Vias

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Solution Overview

Problem

The increasing complexity and cost of packaging semiconductor dies due to the rising density of I/O pads pose challenges in manufacturing, particularly in integrating more functions into smaller semiconductor chips without compromising yield.

Innovation Solution

An Integrated Fan-Out (InFO) package is developed without a laser drill process, utilizing a sacrificial layer to replace the existing dielectric layer, which allows for the formation of through InFO Vias (TIVs) and subsequent packaging steps, thereby eliminating the need for laser drilling and reducing production complexity and cost.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the density of I/O pads is increased to integrate more functions into smaller semiconductor chips, then the functionality and integration level are improved, but the packaging complexity and production cost increase significantly

Engineering Contradiction:
Improveintegration levelVSAvoidpackaging complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

A sacrificial layer is introduced as an intermediary element between the semiconductor die and the packaging structure. This sacrificial layer enables the formation of through-vias that penetrate the molding compound, allowing electrical connections to be established without requiring laser drilling through the entire package structure. The sacrificial layer is temporarily present during manufacturing and is subsequently removed to complete the via formation, thereby simplifying the overall packaging process while maintaining high I/O pad density

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The sacrificial layer is formed and positioned in advance before the molding compound is applied. This preliminary action allows the through-via structures to be pre-configured with precise positioning and dimensional control. The sacrificial layer serves as a template that guides the formation of the via openings, enabling subsequent electrical connections to be made more efficiently without requiring complex post-packaging laser drilling operations

Inventive Principle:
Principle #10Preliminary action

2Reliability

If traditional laser drill process is used to create through-vias in molding compound, then electrical connectivity is achieved, but production cost and manufacturing complexity increase

Engineering Contradiction:
Improveelectrical connectivityVSAvoidproduction cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The traditional laser drilling process is replaced with a mechanical/chemical approach using a sacrificial layer. Instead of using high-energy laser beams to ablate material through the molding compound, the invention uses a sacrificial layer that can be easily removed through simpler processes such as chemical etching or mechanical removal. This substitution eliminates the need for expensive laser equipment and reduces manufacturing complexity while maintaining reliable electrical connectivity through the formed via openings

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Area of moving object

If more I/O pads are packed into smaller areas to reduce chip size, then the chip footprint is reduced, but the packaging yield decreases due to increased difficulty

Engineering Contradiction:
Improvechip footprintVSAvoidpackaging yield
Core Design Contradiction:
Area of moving objectVSProductivity

Solution Approach 1:

The sacrificial layer acts as a mediator that enables precise positioning and formation of through-vias for high-density I/O pads. By providing a structured template during the packaging process, it allows for accurate alignment even when pads are densely packed in small areas. This intermediary structure ensures that electrical connections can be reliably established for each pad, thereby maintaining high packaging yield despite the increased density and reduced chip footprint

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20240379429A1Semiconductor device and manufacturing method of the same
Publication Date: 2024.11.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240379429A1 patent drawing
  • US20240379429A1 patent drawing
  • US20240379429A1 patent drawing

AI summary

Some embodiments of the present disclosure provide a method of manufacturing a semiconductor device. The method includes: forming a carrier; forming a sacrificial layer on the carrier; forming a through via on the sacrificial layer, wherein the through via includes a seed layer and a metal feature; disposing a die on the sacrificial layer, wherein the die has a plurality of metal pillars disposed at a side of the die facing away from the sacrificial layer; forming a molding compound on the sacrificial layer to cover and surround the die and the through via; removing a portion of the molding compound and a portion of the through via above the die to expose the metal feature of the through via; and removing the carrier and sacrificial layer to expose the seed layer of the through via.