Fan-Out Package Stacking With Recessed Interposer for Low-Height PoP
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Solution Overview
Problem
The semiconductor industry faces manufacturing challenges in integrating multiple packages with different or similar functions using new packaging technologies like package on package (PoP), particularly in forming efficient chip packages with high integration density and reliable electrical connections.
Innovation Solution
The process involves forming a chip package by disposing a semiconductor die over a carrier substrate with an interconnection structure, bonding an interposer substrate with a recess around the die, and applying a protective layer, followed by stacking and bonding a package structure, which includes forming conductive elements and underfill layers for electrical and mechanical stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If package on package (PoP) technology is used to integrate multiple packages, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the package structure into multiple discrete layers including first and second packages, interposer substrates, and redistribution layers. Each layer can be independently fabricated and tested before assembly, reducing overall manufacturing complexity while achieving high integration density through vertical stacking.
Solution Approach 2:
The patent implements a nested structure where one package is stacked on another package, with interposer substrates and redistribution layers embedded within the stack. This nested arrangement enables high integration density by utilizing vertical space efficiently while maintaining modular manufacturing processes for each nested component.
2Adaptability or versatility
If multiple packages are integrated using PoP technology, then functional integration is improved, but electrical connection reliability becomes more challenging
Solution Approach 1:
The patent introduces interposer substrates and redistribution layers as intermediary structures between the first and second packages. These intermediaries provide dedicated pathways for electrical connections, improving signal integrity and connection reliability while enabling diverse functional integration across multiple package layers.
Solution Approach 2:
The patent transitions electrical connections from a planar two-dimensional layout to a three-dimensional vertical stack. Conductive vias and interconnect structures extend through the vertical dimension, providing multiple redundant connection paths and improving electrical reliability while enabling higher functional integration density.
3Length of stationary object
If package height is reduced for smaller packages, then area utilization is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent incorporates alignment marks, registration features, and pre-formed conductive vias in each package layer before assembly. These preliminary structures enable precise alignment during the stacking process, maintaining manufacturing precision even as overall package height is reduced and integration density increases.
Solution Approach 2:
The patent employs advanced fabrication techniques that control critical dimensions and material properties at the micro and nanoscale. By precisely controlling via diameter, layer thickness, and material composition, the patent achieves high alignment precision in reduced-height packages through parameter optimization rather than increased physical dimensions.
Data Source
AI summary
Structures and formation methods of chip packages are provided. The method includes disposing a semiconductor die over a carrier substrate. The method also includes disposing an interposer substrate over the carrier substrate. The interposer substrate has a recess that penetrates through opposite surfaces of the interposer substrate. The interposer substrate has interior sidewalls surrounding the semiconductor die, and the semiconductor die is as high as or higher than the interposer substrate. The method further includes forming a protective layer in the recess of the interposer substrate to surround the semiconductor die. In addition, the method includes removing the carrier substrate and stacking a package structure over the interposer substrate.