Double-Layer RDL Fan-Out Packaging for Higher Line Density

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The existing fan-out packaging technologies face limitations in reducing the minimum line width and increasing line density due to the requirement of a substrate in the chip-last packaging method, which also increases manufacturing cycle time.

Innovation Solution

A fan-out packaging structure utilizing a fan-out substrate unit with a double-layer wiring layer and a secondary fan-out unit, where the substrate is replaced by a double-layer redistribution layer (RDL), allowing for increased line density and reduced size, and the centralized preparation method for separate units shortens manufacturing time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If a substrate is used as supporting structure in chip-last packaging method, then structural support is provided, but the overall size of fan-out packaging structure increases and manufacturing cycle time increases

Engineering Contradiction:
Improvestructural supportVSAvoidoverall size of packaging structure
Core Design Contradiction:
StrengthVSVolume of moving object

Solution Approach 1:

The patent removes the traditional substrate from the packaging structure, extracting only the essential supporting function and replacing it with a carrier board that provides minimal support while allowing direct fan-out of signal lines, thereby eliminating the size and time penalties associated with full substrate usage

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent transitions from planar substrate-based packaging to a multi-layer stacked architecture where signal lines fan out in three dimensions through multiple wiring layers, allowing compact vertical integration while maintaining structural integrity without requiring a large substrate

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Strength

If a substrate is used as supporting structure in chip-last packaging method, then structural support is provided, but manufacturing cycle time increases

Engineering Contradiction:
Improvestructural supportVSAvoidmanufacturing cycle time
Core Design Contradiction:
StrengthVSLoss of time

Solution Approach 1:

The patent divides the packaging structure into separate functional modules (carrier board, wiring layers, encapsulation layers, solder bump arrays) that can be manufactured independently and assembled through standardized processes, reducing manufacturing cycle time while maintaining structural support through the carrier board

Inventive Principle:
Principle #1Segmentation

3Ease of manufacture

If traditional packaging structure is used, then manufacturing process is simpler, but line density and minimum line width are limited

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidminimum line width
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent employs multiple wiring layers stacked in the vertical dimension, allowing signal lines to fan out through three-dimensional routing rather than being constrained to a single planar layer, thereby achieving higher line density and smaller minimum line widths while using standardized manufacturing processes for each layer

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

4Quantity of substance

If substrate is replaced by double-layer RDL, then line density increases and size decreases, but structural complexity increases

Engineering Contradiction:
Improveline densityVSAvoidstructural complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent segments the complex multi-layer structure into standardized modular units (carrier board, first and second wiring layers, encapsulation layers, solder bump arrays) that can be manufactured and assembled using established processes, reducing the practical complexity despite the increased line density achieved through the double-layer RDL configuration

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20240047326A1Fan-out packaging structure and method for manufacturing same
Publication Date: 2024.02.08 SJ SEMICONDUCTOR (JIANGYIN) CORP
  • US20240047326A1 patent drawing
  • US20240047326A1 patent drawing
  • US20240047326A1 patent drawing

AI summary

A fan-out packaging structure and a method for manufacturing the same are provided. The structure comprises: a fan-out substrate unit, and a secondary fan-out unit; an effective electrical connection between a second top surface of the fan-out substrate unit and a third bottom surface of the secondary fan-out unit is formed through a second solder array, and the fan-out substrate unit comprises a first wiring layer and a second wiring layer connected by conductive posts. By having a fan-out substrate unit with a double-layer wiring layer as the substrate of the fan-out wiring layer, the present disclosure reduces the achievable minimum line width, thereby increasing the achievable line density of the fan-out package. Meanwhile, replacing the traditional substrate with the double-layer wiring layer, and preparing the fan-out substrate unit and the secondary fan-out unit separately and then combining the two, shortens the time required to prepare the whole structure.