Fan-Out Packaging RDL Sealing Ring for Uniform Electroplating
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Solution Overview
Problem
Conventional fan-out wafer level packaging processes face challenges with limited seed layer thickness due to throughput issues and isotropic etching, leading to non-uniform plating thickness, increased resistance, and reduced electrical performance, which affects production costs and quality.
Innovation Solution
The implementation of a metal sealing ring in the redistribution layer to extend the conductor path and improve local planarization, enhancing the electroplating process efficiency by forming a first and second dielectric layer with via holes and a bump structure, connected via a redistribution layer that includes the metal sealing ring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the Cu seed layer is increased to improve conductivity and reduce resistance, then the overall resistance decreases, but the plating rate slows down and plating thickness uniformity deteriorates
Solution Approach 1:
The patent segments the seed layer into two distinct layers: a thin initial Cu seed layer (5-20 nm) for adhesion and a thicker Al alloy layer (50-200 nm) for conductivity. This segmentation allows each layer to perform its specific function optimally - the Cu layer provides bonding without excessive thickness, while the Al layer provides the necessary conductivity and plating support, thus resolving the contradiction between resistance reduction and plating rate maintenance.
Solution Approach 2:
The patent changes the material parameter from pure Cu to an Al alloy composition (Al-Cu-Si or Al-Cu-Fe) for the thicker seed layer. This parameter change enables the layer to provide both the conductivity needed for fast plating rates and the structural properties for uniform plating thickness, overcoming the limitations of using only Cu at increased thickness.
2Reliability
If the thickness of the Cu seed layer is increased to reduce resistance, then conductivity improves, but isotropic etching of the RDL line increases during etching of the seed layer
Solution Approach 1:
The patent segments the seed layer structure to place the etching-sensitive Cu layer only where needed for adhesion (thin initial layer), while using an Al alloy layer for the bulk thickness. The Al alloy layer is less susceptible to isotropic etching, thus protecting the RDL line width precision while still providing the necessary conductivity for electrical performance.
Solution Approach 2:
The patent applies local quality by using different materials at different locations and depths of the seed layer structure. The thin Cu layer at the interface provides adhesion, while the Al alloy layer above it provides conductivity and etching resistance. This localized material differentiation allows the structure to simultaneously achieve good electrical performance and precise RDL line control.
3Manufacturing precision
If the plating rate is slowed down to improve plating layer quality, then quality improves, but process speed decreases and process reproducibility becomes difficult to achieve
Solution Approach 1:
The patent changes the material composition parameter of the seed layer from pure Cu to an Al alloy (Al-Cu-Si or Al-Cu-Fe) for the thicker layer. This parameter change fundamentally alters the plating characteristics, enabling high plating rates while maintaining excellent plating layer quality and uniformity, thus resolving the contradiction between quality and speed.
Solution Approach 2:
The patent uses a composite seed layer structure combining Cu and Al alloy materials. The Cu layer provides adhesion, while the Al alloy layer provides a substrate that supports high-rate electroplating with excellent quality. This composite approach enables both high process speed and high plating layer quality simultaneously.
4Productivity
If the thickness of the seed layer is increased to allow faster plating rates initially, then initial plating rate increases, but as thickness increases the conductor path becomes insufficient leading to poor electrical performance
Solution Approach 1:
The patent segments the seed layer into a thin Cu layer for adhesion and a thicker Al alloy layer that serves dual purposes: supporting fast plating rates and providing the conductor path for electrical performance. The Al alloy layer's composition and thickness are optimized to maintain sufficient conductivity even at greater thicknesses, thus resolving the contradiction between plating rate and electrical performance.
Solution Approach 2:
The patent changes the material parameter from Cu to Al alloy for the thicker portion of the seed layer. This parameter change allows the layer to maintain adequate electrical conductivity at increased thickness levels while supporting faster plating rates, overcoming the limitation where increased Cu thickness eventually degrades electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves electrical performance, structural stability, and productivity by ensuring even current distribution, reducing overall resistance, and accelerating plating rates, thus enhancing the quality and reducing production costs.
Implementation Method 1
forming a first dielectric layer having a first via hole on a fan-out packaging substrate, forming a redistribution layer (RDL) on the first dielectric layer and the first via hole
Implementation Method 2
a sputtering process is used to form a thin Cu seed layer
Data Source
Figure 1A~1C
Figure 1D~2
Figure 3~4
AI summary
Disclosed is a method of manufacturing a fan-out packaging device, which is a method of manufacturing a packaging device using a wafer or panel level packaging process, the method including forming a first dielectric layer having a first via hole on a fan-out packaging substrate, forming a redistribution layer (RDL) on the first dielectric layer and the first via hole, forming a second dielectric layer having a second via hole formed on the redistribution layer, and forming a bump structure on the second dielectric layer and the second via hole so as to be connected to the redistribution layer, wherein the redistribution layer includes a metal sealing ring to extend a conductor path in a plating process.