Fan-Out RDL Die Stacking Without Package Substrate

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Solution Overview

Problem

Conventional die stacking methods for 3D integrated circuits result in increased footprint and complexity due to the need for multiple encapsulating processes and the use of a package substrate, which hinders the miniaturization and thermal management of stacked dies.

Innovation Solution

The method involves forming integrated fan-out packages with fan-out redistribution layers (RDLs) that extend beyond the edges of device dies, allowing for a single encapsulating process without a package substrate, and using Die-Attach Films (DAF) with low thermal conductivity to manage heat, thereby reducing package thickness and improving electrical performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional die stacking methods with package substrate are used, then electrical connection and structural support are achieved, but package footprint and complexity increase

Engineering Contradiction:
Improveelectrical connectionVSAvoidpackage footprint
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent removes the package substrate from the conventional die stacking structure, extracting the unnecessary component that increases footprint. The dies are directly stacked and connected through through-silicon vias (TSVs) without requiring a separate substrate layer, thereby reducing the overall package area while maintaining electrical connectivity.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent transitions from a planar packaging architecture to a three-dimensional stacked architecture. Multiple dies are vertically stacked with electrical connections established through the thickness direction via TSVs, enabling compact integration in the vertical dimension rather than expanding in the horizontal plane.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If multiple encapsulating processes are used for die stacking, then each die is protected, but manufacturing complexity and process time increase

Engineering Contradiction:
Improvedie protectionVSAvoidmanufacturing process
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple separate encapsulation processes into a single unified encapsulation step. Instead of encapsulating each die individually before stacking, all stacked dies are encapsulated together in one process, reducing manufacturing complexity and process time while still providing comprehensive protection to all dies.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The dies are pre-assembled into a stacked configuration with TSV connections established before the final encapsulation process. This preliminary assembly allows the encapsulation material to be applied once to protect the entire stack, rather than requiring multiple encapsulation steps after individual die processing.

Inventive Principle:
Principle #10Preliminary action

3Strength

If conventional packaging is used, then structural support is provided, but package thickness increases

Engineering Contradiction:
Improvestructural supportVSAvoidpackage thickness
Core Design Contradiction:
StrengthVSLength of stationary object

Solution Approach 1:

The patent employs a thin encapsulation layer that provides necessary structural support and protection without adding significant thickness. The encapsulation material forms a compact shell around the stacked dies, maintaining mechanical integrity while minimizing the overall package thickness to enable miniaturization.

Inventive Principle:
Principle #30Flexible shells and thin films

4Temperature

If standard thermal management is used in stacked dies, then heat dissipation is achieved, but thermal conductivity issues arise in compact packages

Engineering Contradiction:
Improveheat dissipationVSAvoidthermal management
Core Design Contradiction:
TemperatureVSDevice complexity

Solution Approach 1:

The patent uses materials with optimized thermal conductivity properties in the encapsulation and interlayer structures. By selecting composite materials that balance electrical insulation with thermal conduction, the design achieves effective heat dissipation from the stacked dies without requiring complex thermal management systems, managing heat through material selection rather than additional structural complexity.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in a thinner, more compact package with improved electrical performance and reduced thermal conductivity issues, suitable for mobile applications, while minimizing the top-view area and maintaining efficient heat dissipation.

Implementation Method 1

using Die-Attach Films (DAF) with low thermal conductivity to manage heat

Methodology Applied
Scientific EffectThermal insulation: Thermal Insulation

Data Source

PatentUS12080615B2Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors
Publication Date: 2024.09.03 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12080615B2 patent drawing
  • US12080615B2 patent drawing
  • US12080615B2 patent drawing

AI summary

A method includes forming a through-via from a first conductive pad of a first device die. The first conductive pad is at a top surface of the first device die. A second device die is adhered to the top surface of the first device die. The second device die has a surface conductive feature. The second device die and the through-via are encapsulated in an encapsulating material. The encapsulating material is planarized to reveal the through-via and the surface conductive feature. Redistribution lines are formed over and electrically coupled to the through-via and the surface conductive feature.