Fan-Out RF Package Structure for Shorter Antenna Interconnects
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Solution Overview
Problem
Traditional integration methods for 5G/6G communication RF modules result in large volume, high cost, and significant dielectric loss due to long interconnection lines between RF chips and antennas, failing to meet high-frequency signal transmission requirements.
Innovation Solution
A fan-out package structure that embeds an antenna RF module assembly with RF devices in an encapsulation layer, featuring rewiring layers and conductive connections to reduce interconnection line length and dielectric loss, while exposing the antenna array for efficient signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional integration method is used to electrically connect packaged RF chip with antenna array, then RF chip can be connected to antenna, but the module volume becomes large and manufacturing cost increases
Solution Approach 1:
The patent merges the antenna array and RF chip into a single integrated module, eliminating the need for separate packaging and external interconnection. The antenna array is directly formed on the same substrate as the RF chip, creating a unified structure that reduces overall module volume while maintaining reliable electrical connections through short on-substrate traces.
Solution Approach 2:
The patent transitions from a three-dimensional stacked packaging approach to a planar two-dimensional integration approach. By arranging both the antenna array and RF chip on the same substrate plane, the design eliminates vertical stacking height and external interconnection paths, significantly reducing module volume while maintaining all necessary functional connections.
2Reliability
If traditional integration method is used with packaged RF chip, then connection can be established, but manufacturing cost becomes high
Solution Approach 1:
The patent combines multiple manufacturing processes into a single integrated fabrication flow. Both the antenna array and RF chip are manufactured using the same semiconductor fabrication processes on the same substrate, eliminating the need for separate chip packaging, testing, and assembly operations, thereby significantly reducing manufacturing cost.
Solution Approach 2:
The patent performs preliminary integration of the antenna array and RF chip during the semiconductor fabrication process itself, before final packaging. By pre-establishing all electrical connections through on-substrate interconnects during manufacturing, the design eliminates subsequent assembly steps and reduces overall manufacturing complexity and cost.
3Reliability
If traditional integration method is used with long interconnection lines, then RF chip can be connected to antenna, but dielectric loss increases significantly
Solution Approach 1:
The patent reduces interconnection path length by transitioning from three-dimensional vertical stacking with long external traces to a two-dimensional planar layout where both antenna and RF chip reside on the same substrate. This dimensional change creates extremely short on-substrate interconnect paths, minimizing dielectric loss and improving high-frequency signal transmission reliability.
Data Source
AI summary
A fan-out package structure and a fabricating method therefor are provided. The structure includes an encapsulation layer; an antenna RF module assembly and electronic component(s) embedded in the encapsulation layer; a first rewiring layer on a surface of a first side of the encapsulation layer, electrically connected to at least part of the pins of the assembly and to at least part of the pins of the electronic component(s); a second rewiring layer on a surface of a second side of the encapsulation layer, electrically connected to the encapsulation layer-interconnection conductive pillars and to the conductive solder balls/bumps; and conductive solder balls/bumps on a side of the second rewiring layer away from the encapsulation layer. The assembly includes a RF substrate, and an antenna array and RF device(s) arranged thereon. The assembly is embedded in the first side. Encapsulation-layer interconnection conductive pillars are formed in the encapsulation layer.