Fan-Out Semiconductor Device Manufacturing Method
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Solution Overview
Problem
The existing manufacturing methods for semiconductor devices face challenges in achieving a fan-out structure, particularly when a large number of pins are involved, making it difficult to arrange re-wirings and requiring a transition from fan-in to fan-out structures, which complicates the arrangement and connection of external connecting terminals.
Innovation Solution
A manufacturing method that involves forming first and second internal connecting terminals on a semiconductor chip and a supporting board, respectively, with a single insulation layer covering both, and forming a wiring pattern to connect them, followed by a solder resist layer with an opening to expose external connecting terminal areas, allowing for a fan-out structure configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a fan-in structure is used to connect electrode pads to external terminals, then the connection is achieved, but the arrangement becomes complex and stress-induced cracks occur when a large number of pins are involved
Solution Approach 1:
The patent inverts the traditional fan-in structure by implementing a fan-out structure where wiring patterns extend outward from the electrode pads rather than converging toward them. This inversion simplifies the arrangement of external connecting terminals and reduces wiring complexity by allowing terminals to be positioned more freely around the chip perimeter.
Solution Approach 2:
The patent transitions from a two-dimensional fan-in arrangement to a three-dimensional fan-out configuration by utilizing the insulation layer as an intermediate platform. This dimensional change allows wiring patterns to route external terminals in multiple directions outward from the chip center, reducing congestion and simplifying terminal arrangement.
2Reliability
If multiple insulation layers are used to cover internal connecting terminals and form wiring patterns, then electrical insulation is achieved, but stress-induced cracks occur in the connecting terminals
Solution Approach 1:
The patent extracts the electrical insulation function from a multi-layer insulation structure and consolidates it into a single insulation layer that covers both internal connecting terminals and supports wiring patterns. This extraction eliminates the stress accumulation caused by multiple layered structures while maintaining adequate electrical insulation.
Solution Approach 2:
The patent changes the insulation structure from multiple thin layers to a single thicker layer, modifying the physical parameters of the insulation system. This parameter change reduces stress concentration on connecting terminals while providing sufficient electrical insulation, thereby preventing stress-induced cracks.
3Adaptability or versatility
If re-wirings are arranged to convert pitch for fan-in structure, then electrode pad positions are adjusted, but the process becomes complicated and manufacturing efficiency decreases
Solution Approach 1:
The patent inverts the pitch conversion approach by using a fan-out structure where wiring patterns naturally extend outward to accommodate external terminals at different positions. This eliminates the need for complex re-wiring to achieve pitch conversion, as terminals can be positioned freely around the chip perimeter without requiring intricate wiring rearrangements.
Data Source
AI summary
A manufacturing method of a semiconductor device, including a first step of forming a first electrode pad at an external edge part of a semiconductor chip mounting area of a supporting board; a second step of fixing a rear surface of a semiconductor chip having a main surface, the main surface where a second electrode pad is formed, to an inside of an area of the main surface of the supporting board, the area where the first electrode pad is formed; a third step of forming a first internal connecting terminal on the first electrode pad, and forming a second internal connecting terminal on the second electrode pad; and a fourth step of forming a first insulation layer on the main surface of the supporting board.