Fan-Out Semiconductor Package with Thermal Filling and EMI Shielding
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Solution Overview
Problem
Conventional semiconductor packages face challenges with fine pitch pad alignment due to chip drift during epoxy molding, high thermal resistance leading to heat dissipation issues, and high costs and low productivity in flip chip Ball Grid Array packaging.
Innovation Solution
A semiconductor package with a fan-out structure incorporating an interconnect portion, a semiconductor chip bonded via flip chip, a filling member for thermal conductivity, and a membrane member for electromagnetic interference shielding, along with a method involving an insulating and interconnect layer substrate, underfilling, and coating to prevent misalignment and enhance heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If epoxy molding compound is used to seal and protect the semiconductor chip, then the chip is protected from environmental damage, but thermal resistance increases and heat dissipation becomes difficult
Solution Approach 1:
The patent divides the packaging structure into multiple functional layers: EMC for protection, thermal interface material for heat transfer, and heat dissipation structures. This segmentation allows each layer to perform its specialized function - protection, thermal conduction, and heat dissipation respectively - resolving the contradiction between protection and heat dissipation.
Solution Approach 2:
The patent employs composite material structures including thermal interface materials combined with heat dissipation structures, and multi-layer packaging configurations. These composite structures integrate materials with different thermal properties to achieve both protection and effective heat dissipation simultaneously.
2Reliability
If conventional EMC molding process is used, then chip protection is achieved, but chip drift occurs causing misalignment between chip pad and circuit
Solution Approach 1:
The patent applies preliminary actions by pre-positioning the chip with accurate alignment markers before EMC molding, and using alignment structures that are formed prior to the molding process. This ensures precise pad alignment is established before the molding occurs, preventing drift-related misalignment.
Solution Approach 2:
The patent introduces alignment markers and alignment structures as intermediary elements between the chip and the molding process. These intermediaries serve as reference points that maintain precise alignment during the EMC molding process, preventing chip drift from causing misalignment.
3Reliability
If flip chip BGA package is used for individual chip packaging, then chip protection and connection are achieved, but productivity decreases and manufacturing cost increases
Solution Approach 1:
The patent merges multiple packaging operations into a single integrated process. By combining chip mounting, underfill application, and EMC molding into one consolidated workflow, the patent achieves flip chip BGA-level connection quality while maintaining higher productivity through process integration and reduced handling steps.
4Volume of moving object
If chip size is reduced for miniaturization, then device density increases, but pitch of electrode pads becomes smaller making alignment more difficult
Solution Approach 1:
The patent addresses fine pitch alignment challenges by introducing alignment markers and reference structures in additional dimensions. These multi-dimensional alignment features enable precise positioning of small-pitch pads through multi-axis alignment procedures, overcoming the difficulties posed by miniaturized chip dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a thin, cost-effective semiconductor package with improved heat dissipation and alignment, reduced manufacturing complexity, and increased productivity by using a fan-out structure and membrane member, addressing the limitations of conventional packaging technologies.
Implementation Method 1
a filling member filling between the semiconductor chip and the interconnect portion
Implementation Method 2
a membrane member coated to cover one surfaces of the semiconductor chip, the filling member, and the interconnect portion
Data Source
AI summary
A semiconductor package comprising a fan-out structure and a manufacturing method therefor are disclosed. A semiconductor package according to an embodiment of the present invention comprises: a wiring unit comprising an insulation layer and a wiring layer; a semiconductor chip mounted on the wiring unit and coupled to the wiring layer by flip-chip bonding; a filling member for filling a gap between the semiconductor chip and the wiring unit; and a film member for performing coating so as to cover one surface of each of the semiconductor chip, the filling member, and the wiring unit.