3D Fan-Out Semiconductor Packages With Redistribution Structures
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Solution Overview
Problem
Conventional wafer-level packaging is restricted to a fan-in configuration, limiting the arrangement and size of semiconductor device components as device sizes shrink, as components outside the periphery are not supported and are typically removed during singulation.
Innovation Solution
The method involves forming semiconductor device packages with a carrier and redistribution structures that allow for a fan-out configuration, where electrical interconnects extend laterally and vertically, enabling components to be positioned outside the device periphery, and applying a molding material to create a molded structure that covers and supports the device, allowing for a three-dimensional fan-out configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional wafer-level packaging with fan-in configuration is used, then manufacturing process is simple, but component arrangement flexibility is limited and package size cannot be reduced further
Solution Approach 1:
The patent transitions from a planar fan-in configuration to a three-dimensional fan-out configuration by extending electrical interconnects vertically and laterally. The redistribution structures include vertical vias and lateral traces that route signals in multiple dimensions, allowing components to be positioned outside the device periphery while maintaining compact packaging.
Solution Approach 2:
The package structure is divided into multiple functional layers including first and second redistribution structures with separate electrical interconnect systems. The first redistribution structure handles vertical interconnects while the second handles lateral routing, allowing independent optimization of each segment for its specific function.
2Speed
If device size is reduced to enhance processing speeds, then processing performance improves, but component arrangement options are limited due to fan-in configuration restrictions
Solution Approach 1:
By implementing three-dimensional fan-out with vertical vias and lateral traces, the patent enables component placement in directions beyond the original device periphery. This multi-dimensional routing provides flexibility in component arrangement even as the active device area shrinks to improve processing speed.
3Adaptability or versatility
If fan-out configuration with components outside periphery is implemented, then component arrangement flexibility increases, but manufacturing complexity increases
Solution Approach 1:
The carrier is prepared in advance with pre-formed first and second redistribution structures before the semiconductor device is mounted. The electrical interconnects are already in place with proper alignment features, so when the device is attached, the fan-out configuration is automatically achieved without complex post-assembly routing operations.
Solution Approach 2:
The carrier serves as an intermediary substrate that holds both the semiconductor device and the redistribution structures. This intermediate platform simplifies manufacturing by providing a common reference frame for aligning the device with the pre-formed electrical interconnects, reducing the complexity of creating fan-out configurations.
4Volume of moving object
If three-dimensional fan-out configuration is used, then package size is reduced and component flexibility increases, but structural stability may be compromised
Solution Approach 1:
The patent employs a composite structure combining the semiconductor device, carrier substrate, and redistribution structures with electrical interconnects. This composite architecture provides both the compact three-dimensional fan-out configuration and the structural stability needed to support components positioned outside the original device periphery.
Data Source
AI summary
In one embodiment, a method of forming a semiconductor device package includes: (1) providing a carrier and a semiconductor device including an active surface; (2) forming a first redistribution structure including a first electrical interconnect extending laterally within the first structure and a plurality of second electrical interconnects extending vertically from a first surface of the first interconnect, each second interconnect including a lower surface adjacent to the first surface and an upper surface opposite the lower surface; (3) disposing the device on the carrier such that the active surface is adjacent to the carrier; (4) disposing the first structure on the carrier such that the upper surface of each second interconnect is adjacent to the carrier, and the second interconnects are positioned around the device; and (5) forming a second redistribution structure adjacent to the active surface, and including a third electrical interconnect extending laterally within the second structure.