Fan-Out Semiconductor Package With Vertical Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional wafer-level packaging restricts semiconductor device stacking due to its fan-in configuration, which limits the arrangement and spacing of electrical contacts, making it inadequate for shrinking device sizes and increased functionality in compact electronic products.
Innovation Solution
A semiconductor device package with a patterned conductive layer extending laterally and vertically, allowing for a fan-out configuration that provides greater flexibility in electrical connections and supports stacking by exposing connecting elements at the periphery, enabling a three-dimensional fan-out configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional wafer-level packaging with fan-in configuration is used, then manufacturing process is simplified, but device stacking capability is limited and footprint area cannot be reduced sufficiently
Solution Approach 1:
The patent transitions from traditional two-dimensional fan-in packaging to three-dimensional fan-out packaging by extending conductive layers vertically and laterally. The interconnection unit includes patterned conductive layers at multiple levels (first, second, and third patterned conductive layers) that extend in both horizontal and vertical dimensions, enabling stacking of semiconductor devices while maintaining electrical connectivity. This dimensional expansion allows devices to be stacked above and below the interconnection unit, significantly improving stacking capability while preserving manufacturing feasibility through established semiconductor fabrication processes.
2Device complexity
If fan-in configuration is used, then electrical contacts are restricted to area within device periphery, but this limits flexibility in electrical connection arrangement
Solution Approach 1:
The patent extends the electrical connection area by adding vertical dimension to the conductive pathways. The patterned conductive layers are arranged at different heights (first, second, and third layers) and extend laterally beyond the semiconductor device periphery. This allows electrical contacts to be positioned both within and outside the device footprint, providing flexible arrangement options for input and output connections while increasing the effective electrical contact area available for interconnections.
3Area of stationary object
If semiconductor devices are stacked to reduce footprint, then space efficiency is improved, but conventional packaging lacks adequate stacking functionality
Solution Approach 1:
The patent enables three-dimensional stacking by creating an interconnection unit with multiple patterned conductive layers extending in vertical and lateral directions. The interconnection unit serves as a platform that can accommodate semiconductor devices stacked above and below it, with electrical interconnects providing pathways through the stack. This dimensional approach reduces the footprint area occupied by multiple devices while providing robust stacking functionality through the multi-layer interconnection structure.
Solution Approach 2:
The patent divides the packaging structure into distinct functional segments: the interconnection unit with its multi-layer conductive structure, the semiconductor devices to be stacked, and the package body enclosing them. This segmentation allows each component to be optimized independently - the interconnection unit for electrical connectivity, the devices for their respective functions, and the package body for protection and structural support - while working together to achieve compact stacked configuration.
Data Source
AI summary
An embodiment of a semiconductor device package includes: (1) an interconnection unit including a patterned conductive layer; (2) an electrical interconnect extending substantially vertically from the conductive layer; (3) a semiconductor device adjacent to the interconnection unit and electrically connected to the conductive layer; (4) a package body: (a) substantially covering an upper surface of the interconnection unit and the device; and (b) defining an opening adjacent to an upper surface of the package body and exposing an upper surface of the interconnect; and (5) a connecting element electrically connected to the device, substantially filling the opening, and being exposed at an external periphery of the device package. The upper surface of the interconnect defines a first plane above a second plane defined by at least a portion of the upper surface of the interconnection unit, and below a third plane defined by the upper surface of the package body.