Thin Fan-Out Multi-Chip Stacked Package Structure
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing multi-chip stack package structure faces challenges in reducing thickness due to the requirement of substrate thickness and wiring arc height, leading to issues like wire sweep during encapsulation.
Innovation Solution
A thin fan-out multi-chip stacked package structure is developed, incorporating a chip stack, dummy spacer, bonding wires, encapsulant, and redistribution layer structure, which alleviates wire sweep by forming a flat surface with polished cross-sectional surfaces, allowing for an ultra-thin package thickness close to the chip stack height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If traditional multi-chip stack package structure is used with substrate and arc-shaped wiring, then electrical connection between chips and substrate is achieved, but package thickness cannot be reduced due to substrate thickness and wiring arc height requirements
Solution Approach 1:
The patent transitions from planar arc-shaped wiring to vertical three-dimensional wiring structure. Bonding wires are configured with vertical wire segments that extend perpendicular to the chip stack, eliminating the need for substrate and arc-shaped wiring. This dimensional change enables ultra-thin package structure while maintaining electrical connectivity.
Solution Approach 2:
A dummy spacer is introduced as an intermediary component to support the vertical bonding wires during the encapsulation process. The dummy spacer prevents wire sweep by providing mechanical support to the vertical wire segments, ensuring wiring reliability in the ultra-thin package structure.
2Reliability
If long bonding wires are used in traditional package structure, then electrical connection is achieved, but wire sweep and short-circuit issues occur easily during encapsulation
Solution Approach 1:
The bonding wires are configured with curved wire segments that connect the vertical wire segments to the chip electrodes. The curved configuration allows the wires to clear the encapsulation mold and avoid short-circuit issues during encapsulation, while the vertical orientation minimizes wire length compared to traditional arc-shaped wiring.
Solution Approach 2:
The dummy spacer serves as a temporary support structure during encapsulation, preventing wire sweep of the vertical bonding wires. After encapsulation, the dummy spacer is removed, having fulfilled its protective function during the critical encapsulation process.
3Length of stationary object
If substrate and arc-shaped wiring are used, then complete bonding wire connection is achieved, but total thickness of package structure is increased
Solution Approach 1:
The substrate is completely removed from the package structure. Instead of using a substrate as the base platform, chips are stacked directly on a temporary carrier plate, and vertical bonding wires provide electrical connection without requiring substrate integration. This extraction of the substrate enables ultra-thin package structure.
Solution Approach 2:
The temporary carrier plate is used during the packaging process to hold the chip stack, then discarded after the package is complete. This allows the final package structure to consist only of the essential components (chips, bonding wires, encapsulant) without the added thickness of a permanent substrate.
Data Source
AI summary
A thin fan-out multi-chip stacked package structure including a plurality of stacked chips is provided. The electrodes of the stacked chips and the active surface of the top chip are exposed. A dummy spacer is disposed on the active surface. Each bonding wire has a bonding thread bonded to a chip electrode and an integrally-connected vertical wire segment. A flat encapsulant encapsulates the chip stacked structure and the bonding wires. Polished cross-sectional surfaces of the bonding wires and a surface of the dummy spacer are exposed by the flat surface of the encapsulant. A redistribution layer structure is formed on the flat surface. A passivation layer covers the flat surface and the surface of the dummy spacer but exposes the polished cross-sectional surfaces. Fan-out circuits are formed on the passivation layer and are connected to the polished cross-sectional surfaces of the bonding wires.